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order this document by MC68HC16Z1ts/d rev. 3 m this document contains information on a new product. specifications and information herein are subject to change without notice. ?motorola inc., 1992, 1996 motorola semiconductor technical data MC68HC16Z1 technical summary 16-bit microcontroller 1 introduction the MC68HC16Z1 is a high-speed 16-bit control unit that is upwardly code compatible with m68hc11 controllers. it is a member of the m68300/68hc16 family of modular microcontrollers. m68hc16 controllers are built up from standard modules that interface through a common internal bus. standardization facilitates rapid development of devices tailored for specific applications. the MC68HC16Z1 incorporates a true 16-bit central processing unit (cpu16), a system integration module (sim), an 8/10-bit analog-to-digital converter (adc), a queued serial module (qsm), a general- purpose timer (gpt), and a 2048-byte standby ram (sram). these modules are interconnected by the intermodule bus (imb). maximum system clock for the MC68HC16Z1 is 16.78 mhz. a phase-locked loop circuit synthesizes the clock from a frequency reference. either a crystal (nominal frequency: 32.768 khz) or an externally generated signal can be used. system hardware and software support changes in clock rate during op- eration. because the MC68HC16Z1 is a fully static design, register and memory contents are not affect- ed by clock rate changes. high-density complementary metal-oxide semiconductor (hcmos) architecture makes the basic power consumption of the MC68HC16Z1 low. power consumption can be minimized by stopping the system clock. the m68hc16 instruction set includes a low-power stop (lpstop) command that efficiently im- plements this capability. .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 2 MC68HC16Z1ts/d table 1 ordering information device package temperature range ( c) reference frequency shipping method order number 132-pin plastic surface mount ?0 to 85 16.78 mhz 36 per tray xc16z1cfc16 2 per tray spakxc16z1cfc16 20 mhz 36 per tray xc16z1cfc20 2 per tray spakxc16z1cfc20 25 mhz 36 per tray xc16z1cfc25 2 per tray spakxc16z1cfc25 ?0 to 105 16.78 mhz 36 per tray xc16z1vfc16 2 per tray spakxc16z1vfc16 20 mhz 36 per tray xc16z1vfc20 2 per tray spakxc16z1vfc20 25 mhz 36 per tray xc16z1vfc25 2 per tray spakxc16z1vfc25 ?0 to 125 16.78 mhz 36 per tray xc16z1mfc16 2 per tray spakxc16z1mfc16 20 mhz 36 per tray xc16z1mfc20 2 per tray spakxc16z1mfc20 25 mhz 36 per tray xc16z1mfc25 2 per tray spakxc16z1mfc25 132-pin molded carrier ring ?0 to 85 16.78 mhz 10 per tube xc16z1cfd16 20 mhz 10 per tube xc16z1cfd20 25 mhz 10 per tube xc16z1cfd25 ?0 to 105 16.78 mhz 10 per tube xc16z1vfd16 20 mhz 10 per tube xc16z1vfd20 25 mhz 10 per tube xc16z1vfd25 ?0 to 125 16.78 mhz 10 per tube xc16z1mfd16 20 mhz 10 per tube xc16z1mfd20 25 mhz 10 per tube xc16z1mfd25 144-pin plastic surface mount ?0 to 85 16.78 mhz 44 per tray xc16z1cfv16 2 per tray spakxc16z1cfv16 20 mhz 44 per tray xc16z1cfv20 2 per tray spakxc16z1cfv20 25 mhz 44 per tray xc16z1cfv25 2 per tray spakxc16z1cfv25 ?0 to 105 16.78 mhz 44 per tray xc16z1vfv16 2 per tray spakxc16z1vfv16 20 mhz 44 per tray xc16z1vfv20 2 per tray spakxc16z1vfv20 25 mhz 44 per tray xc16z1vfv25 2 per tray spakxc16z1vfv25 ?0 to 125 16.78 mhz 44 per tray xc16z1mfv16 2 per tray spakxc16z1mfv16 20 mhz 44 per tray xc16z1mfv20 2 per tray spakxc16z1mfv20 25 mhz 44 per tray xc16z1mfv25 2 per tray spakxc16z1mfv25 144-pin molded carrier ring ?0 to 85 16.78 mhz 13 per tube xc16z1cfm16 20 mhz 13 per tube xc16z1cfm20 25 mhz 13 per tube xc16z1cfm25 ?0 to 105 16.78 mhz 13 per tube xc16z1vfm16 20 mhz 13 per tube xc16z1vfm20 25 mhz 13 per tube xc16z1vfm25 ?0 to 125 16.78 mhz 13 per tube xc16z1mfm16 20 mhz 13 per tube xc16z1mfm20 25 mhz 13 per tube xc16z1mfm25 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 3 section page 1 introduction 1 1.1 features ...................................................................................................................................... 4 1.2 pin description ............................................................................................................................ 8 1.3 signal description ..................................................................................................................... 10 1.4 internal register address map .................................................................................................. 13 1.5 pseudolinear memory maps ...................................................................................................... 14 1.6 intermodule bus ........................................................................................................................ 15 2 cpu16 16 2.1 overview ................................................................................................................................... 16 2.2 m68hc11 compatibility ............................................................................................................. 16 2.3 programmer's model ................................................................................................................. 17 2.4 data types ................................................................................................................................ 19 2.5 addressing modes ..................................................................................................................... 19 2.6 instruction set ........................................................................................................................... 20 2.7 exceptions ................................................................................................................................. 39 3 system integration module 42 3.1 system configuration and protection ........................................................................................ 45 3.2 system configuration ................................................................................................................ 45 3.3 system protection ..................................................................................................................... 47 3.4 system clock ............................................................................................................................ 49 3.5 external bus interface ............................................................................................................... 53 3.6 resets ....................................................................................................................................... 64 3.7 interrupts ................................................................................................................................... 67 3.8 factory test block ..................................................................................................................... 69 4 analog-to-digital converter module 71 4.1 analog subsystem .................................................................................................................... 71 4.2 digital control subsystem ......................................................................................................... 71 4.3 bus interface subsystem .......................................................................................................... 71 4.4 adc registers ........................................................................................................................... 73 5 queued serial module 80 5.1 qsm registers .......................................................................................................................... 81 5.2 qspi submodule ....................................................................................................................... 85 5.3 sci submodule ......................................................................................................................... 92 6 standby ram module 99 6.1 sram register block ................................................................................................................ 99 6.2 sram registers ........................................................................................................................ 99 6.3 sram operation ..................................................................................................................... 100 7 general-purpose timer module 102 7.1 capture/compare unit ............................................................................................................ 103 7.2 pulse-width modulator ............................................................................................................ 105 7.3 gpt registers ......................................................................................................................... 106 8 electrical characteristics 114 9 summary of changes 140 table of contents .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 4 MC68HC16Z1ts/d 1.1 features ?cpu16 ? 16-bit architecture ? full set of 16-bit instructions ? three 16-bit index registers ? two 16-bit accumulators ? control-oriented digital signal processing capability ? 1 megabyte of program memory and 1 megabyte of data memory ? high-level language support ? fast interrupt response time ? background debugging mode ? fully static operation ?system integration module ? external bus support ? programmable chip-select outputs ? system protection logic ? watchdog timer, clock monitor, and bus monitor ? two 8-bit dual function ports ? one 7-bit dual function port ? phase-locked loop (pll) clock system ?8/10-bit analog-to-digital converter ? eight channels, eight result registers ? eight automated modes ? three result alignment modes ? one 8-bit digital input port ?queued serial module ? enhanced serial communication interface ? queued serial peripheral interface ? one 8-bit dual function port ?general-purpose timer ? two 16-bit free-running counters with prescaler ? three input capture channels ? four output compare channels ? one input capture/output compare channel ? one pulse accumulator/event counter input ? two pulse width modulation outputs ? one 8-bit dual function port ? two optional discrete inputs ? optional external clock input ?standby ram ? 1024-byte static ram ? external standby voltage supply input .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 5 figure 1 MC68HC16Z1 block diagram z1 block pada5/an5 pada7/an7 pada4/an4 pada6/an6 cpu16 adc imb pada0/an0 pada1/an1 pada2/an2 port ad txd pcs2 sck miso mosi control pcs1 pada3/an3 pcs0 v dda pcs3 bkpt /dsclk ipipe1/dsi ipipe0/dso dsi dso ipipe0 ipipe1 bkpt irq [7:1 ] addr[23:0] control port f port c fc2 fc1 fc0 bg br bgack modclk addr[23:19] clock ebi cs [10:0 ] bgack /cs2 bg /cs1 br /cs0 r/w reset halt berr clkout xtal extal chip selects csboot quot test freeze/quot tstme /tsc control tsc pc0/fc0/cs3 pc1/fc1/cs4 pc2/fc2/cs5 pc3/addr19/cs6 pc4/addr20/cs7 pc5/addr21/cs8 pc6/addr22/cs9 addr23/cs10 pf7/irq7 pf6/irq6 pf5/irq5 pf4/irq4 pf3/irq3 pf2/irq2 pf1/irq1 pf0/modclk control port e siz1 pe7/siz1 siz0 pe6/siz0 dsack0 pe0/dsack0 dsack1 pe1/dsack1 avec pe2/avec as pe5/as pe3 pe4/ds xfc v ddsyn control ds control dsclk data[15:0] pgp5/oc3/oc1 pgp7/ic4/oc5/oc1 pgp4/oc2/oc1 pgp6/oc4/oc1 pgp0/ic1 pgp1/ic2 pgp2/ic3 port gp pgp3/oc1 pqs5/pcs2 pqs7/txd pqs4/pcs1 pqs6/pcs3 pqs0/miso pqs1/mosi pqs2/sck port qs control pqs3/ss /pcs0 pai v ssa v stby v rl v rh sram gpt v stby qsm pai control pwma pwmb pclk ic4/oc5/oc1 oc4/oc1 oc3/oc1 oc2/oc1 oc1 ic3 ic2 ic1 pwma pwmb pclk sim tstme data[15:0] addr[18:0] v dd v ss freeze .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 6 MC68HC16Z1ts/d figure 2 MC68HC16Z1 132-pin package pin assignments z1 132-pin qfp MC68HC16Z1 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 data9 v dde v sse data12 data13 data14 data15 addr0 addr2 v dde v sse addr3 addr4 addr5 addr6 addr7 addr9 addr10 addr11 addr12 addr14 addr15 addr16 addr17 v sse v dda v ssa pada0/an0 pada1/an1 pada2/an2 pada3/an3 pada4/an4 pada5/an5 pc0/fc0/cs3 csboot data0 data1 v ssi data4 data5 data6 data8 pqs7/txd v ssi v dde pe1/dsack1 pe0/dsack0 pe2/avec pe4/ds pe5/as v sse pc2/fc2/cs5 pc1/fc1/cs4 v dde 51 17 117 16 15 14 13 12 11 10 9 8 7 6 5 4 3 131 130 129 128 127 126 125 124 123 122 121 120 119 118 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 pada6/an6 pada7/an7 v stby v ssi xfc v sse freeze/quot bkpt /dsclk pf1/irq1 r/w pe7/siz1 pqs6/pcs3 pqs5/pcs2 pqs4/pcs1 pqs3/ss /pcs0 pqs2/sck pqs1/mosi pqs0/miso v sse pgp1/ic2 pgp2/ic3 pgp3/oc1 pgp4/oc2/oc1 pgp6/oc4/oc1 pgp7/ic4/oc5/oc1 pai pwma pgp5/oc3/oc1 bg /cs1 pclk v rl bgack /cs2 pc3/addr19/cs6 pc4/addr20/cs7 pc5/addr21/cs8 pc6/addr22/cs9 eclk/addr23/cs10 v dde v sse pe6/siz0 pf0/modclk pf2/irq2 pf3/irq3 pf4/irq4 pf5/irq5 pf6/irq6 pf7/irq7 berr halt reset ipipe1/dsi extal v ddsyn xtal 2 1 132 v dde pwmb v ssi v ddi v dde pgp0/ic1 rxd addr8 addr13 v dde addr18 v rh v ddi clkout tstme /tsc ipipe0/dso v sse data10 data11 data7 data3 data2 br /cs0 addr1 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 7 figure 3 MC68HC16Z1 144-pin package pin assignments z1 144-pin qfp bg /cs1 nc bgack /cs2 pc3/addr19/cs6 pc4/addr20/cs7 pc5/addr21/cs8 pc6/addr22/cs9 addr23/cs10 v dde v sse pclk pwma pai pgp7/ic4/oc5/oc1 pgp6/oc4/oc1 pgp5/oc3/oc1 nc pgp4/oc2 pgp3/oc1 pgp1/ic2 pgp0/ic1 v dde v sse pqs0/miso pqs1/mosi pqs2/sck MC68HC16Z1 v sse pe7/siz1 r/w pf0/modclk pf1/irq1 pf2/irq2 pf3/irq3 pf4/irq4 pf5/irq5 pf6/irq6 pf7/irq7 berr halt reset ipipe1/dsi ipipe0/dso nc freeze/quot clkout v dde xfc nc v ssi extal v ddsyn xtal v stby pada7/an7 pada6/an6 v rlp nc pqs3/ss /pcs0 pqs4/pcs1 pqs5/pcs2 pqs6/pcs3 nc 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 107 108 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 31 32 33 34 35 36 pc2/fc2/cs5 pc1/fc1/cs4 v dde v sse pc0/fc0/cs3 csboot data0 data1 nc v ssi nc data4 data5 data7 data8 data9 v dde nc v sse data11 data12 data13 data14 data15 addr0 pe0/dsack0 pe1/dsack1 pe2/avec pe4/ds pe5/as v dde addr1 addr2 v dde v sse addr3 addr4 addr5 addr6 addr7 addr8 nc v ssi nc addr9 addr10 addr11 addr13 addr14 nc addr15 addr16 addr17 v sse v dda v ssa pada0/an0 pada1/an1 pada2/an2 pada3/an3 pada4/an4 pada5/an5 143 144 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 65 68 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 66 67 69 70 71 72 addr12 addr18 v dde v ddi v sse tstme /tsc bkpt /dsclk pe6/siz0 data10 data6 data3 data2 br /cs0 pwmb v ddi v ssi rxd pqs7/txd pgp2/ic3 v rhp .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 8 MC68HC16Z1ts/d 1.2 pin description the following table shows MC68HC16Z1 pins and their characteristics. all inputs detect cmos logic levels. all inputs can be put in a high-impedance state, but the method of doing this differs depending upon pin function. refer to the table, MC68HC16Z1 driver types, for a description of output drivers. an entry in the discrete i/o column of the MC68HC16Z1 pin characteristics table indicates that a pin has an alternate i/o function. the port designation is given when it applies. refer to the MC68HC16Z1 block diagram for information about port organization. table 2 MC68HC16Z1 pin characteristics pin mnemonic output driver input synchronized input hysteresis discrete i/o port designation addr23/cs10 /eclk a y n o addr[22:19]/cs[9:6] a y n o c[6:3] addr[18:0] a y n an[7:0] 1 ? y n i ada[7:0] as b y n i/o e5 avec b y n i/o e2 berr b y n ? ? bg /cs1 b ? ? ? ? bgack /cs2 b y n ? ? bkpt /dsckl ? y y ? ? br /cs0 b y n o separate clkout a ? ? ? ? csboot b ? ? ? ? data[15:0] 1 aw y n ? ? ds b y n i/o e4 dsack1 b y n i/o e1 dsack0 b y n i/o e0 dsi/ipipe1 a y y ? separate dso/ipipe0 a ? separate extal 2 ? ? special ? ? fc[2:0]/cs[5:3] a y n o c[2:0] freeze/quot a ? ? ? ? halt bo y n ? ? ic4/oc5 a y y i/o gp4 ic[3:1] a y y i/o gp[7:5] irq[7:1] b y y i/o f[7:1] miso bo y y i/o qs0 modclk 1 b y n i/o f0 mosi bo y y i/o qs1 oc[4:1] a y y i/o gp[3:0] pai 3 ? y y i separate pclk 3 ? y y i separate pcs0/ss bo y y i/o qs3 pcs[3:1] bo y y i/o qs[6:4] pwma, pwmb 4 a ? ? o separate .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 9 notes 1. data[15:0] are synchronized during reset only. modclk, mcci and adc pins are synchronized only when used as input port pins. 2. extal, xfc, and xtal are clock reference connections. 3. pai and pclk can be used for discrete input, but are not part of an i/o port. 4. pwma and pwmb can be used for discrete output, but are not part of an i/o port. 5. v rh and v rl are adc reference voltage inputs. r/w a y n ? ? reset bo y y ? ? rxd ? n n ? ? sck bo y y i/o qs2 siz[1:0] b y n i/o e[7:6] tstme /tsc ? y y ? ? txd bo y y i/o qs7 v rh 5 ? ? ? ? ? v rl 5 ? ? ? ? ? xfc 2 ? ? ? special ? xtal 2 ? ? ? special ? table 3 MC68HC16Z1 power connections v stby standby ram power/clock synthesizer power v ddsyn clock synthesizer power v dda /v ssa a/d converter power v sse /v dde external periphery power (source and drain) v ssi /v ddi internal module power (source and drain) table 4 MC68HC16Z1 driver types type i/o description a o output-only signals that are always driven; no external pull-up required aw o type a output with weak p-channel pull-up during reset b o three-state output that includes circuitry to pull up output before high impedance is es- tablished, to ensure rapid rise time. an external holding resistor is required to maintain logic level while the pin is in the high-impedance state. bo o type b output that can be operated in an open-drain mode table 2 MC68HC16Z1 pin characteristics (continued) pin mnemonic output driver input synchronized input hysteresis discrete i/o port designation .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 10 MC68HC16Z1ts/d 1.3 signal description use the following tables as a quick reference to MC68HC16Z1 signal type and function. table 5 MC68HC16Z1 signal characteristics signal name mcu module signal type active state addr[23:0] sim bus ? an[7:0] adc input ? as sim output 0 avec sim input 0 berr sim input 0 bg sim output 0 bgack sim input 0 bkpt cpu16 input 0 br sim input 0 clkout sim output ? cs[10:0] sim output 0 csboot sim output 0 data[15:0] sim bus ? ds sim output 0 dsack[1:0] sim input 0 dsclk cpu16 input serial clock dsi cpu16 input (serial data) dso cpu16 output (serial data) extal sim input ? fc[2:0] sim output ? freeze sim output 1 halt sim input/output 0 ic[4:1] gpt input ? ipipe0 cpu16 output ? ipipe1 cpu16 output ? irq[7:1] sim input 0 miso qsm input/output ? modclk sim input ? mosi qsm input/output ? oc[5:1] gpt output ? pada[7:0] adc input (port) pai gpt input ? pc[6:0] sim output (port) pe[7:0] sim input/output (port) pf[7:0] sim input/output (port) pgp[7:0] gpt input/output (port) pqs[7:0] qsm input/output (port) pclk gpt input pcs[3:0] qsm input/output ? pwma, pwmb gpt output ? quot sim output ? .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 11 r/w sim output 1/0 reset sim input/output 0 rxd qsm input ? sck qsm input/output ? siz[1:0] sim output ? ss qsm input 0 tsc sim input ? tstme sim input 0 txd qsm output ? v rh adc input v rl adc input xfc sim input ? xtal sim output ? table 6 MC68HC16Z1 signal function signal name mnemonic function address strobe as indicates that a valid address is on the address bus autovector avec requests an automatic vector during interrupt acknowledge bus error berr indicates that a bus error has occurred bus grant bg indicates that the mcu has relinquished the bus bus grant acknowledge bgack indicates that an external device has assumed bus mastership breakpoint bkpt signals a hardware breakpoint to the cpu bus request br indicates that an external device requires bus mastership chip selects cs[10:0] select external devices at programmed addresses boot chip select csboot chip select for external boot start-up rom address bus addr[19:0] 20-bit address bus used by cpu16 address bus addr[23:20] 4 msb on imb, test only, outputs follow addr19 adc analog input an[7:0] inputs to adc mux system clockout clkout system clock output data bus data[15:0] 16-bit data bus data strobe ds during a read cycle, indicates that an external device should place valid data on the data bus. during a write cycle, indicates that valid data is on the data bus halt halt suspend external bus activity interrupt request level irq[7:1] provides an interrupt priority level to the cpu data and size acknowledge dsack[1:0] provide asynchronous data transfers and dynamic bus sizing peripheral chip select pcs[3:0] qspi peripheral chip selects reset reset system reset test mode enable tstme hardware enable for sim test mode development serial in, out, clock dsi, dso, dsclk serial i/o and clock for background debug mode crystal oscillator extal, xtal connections for clock synthesizer circuit reference; a crystal or an external oscillator can be used function codes fc[2:0] identify processor state and current address space table 5 MC68HC16Z1 signal characteristics (continued) signal name mcu module signal type active state .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 12 MC68HC16Z1ts/d freeze freeze indicates that the cpu has entered background mode instruction pipeline pipe[1:0] indicate instruction pipeline activity master in slave out miso serial input to qspi in master mode; serial output from qspi in slave mode clock mode select modclk selects the source and type of system clock master out slave in mosi serial output from qspi in master mode; serial input to qspi in slave mode port ada pada[7:0] adc digital input port signals port c pc[6:0] sim digital output port signals port e pe[7:0] sim digital i/o port signals port f pf[7:0] sim digital i/o port signals port gp pgp[7:0] gpt digital i/o port signals port qs pqs[7:0] qsm digital i/o port signals quotient out quot provides the quotient bit of the polynomial divider read/write r/w indicates the direction of data transfer on the bus sci receive data rxd serial input to the sci qspi serial clock sck clock output from qspi in master mode; clock input to qspi in slave mode size siz[1:0] indicates the number of bytes to be transferred during a bus cycle slave select ss causes serial transmission when qspi is in slave mode; causes mode fault in master mode three-state control tsc places all output drivers in a high-impedance state sci transmit data txd serial output from the sci adc reference voltage v rh,vrl provide precise reference for a/d conversion external filter capacitor xfc connection for external phase-locked loop filter capacitor crystal oscillator extal, xtal connections for clock synthesizer circuit reference; a crystal or an external oscillator can be used function codes fc[2:0] identify processor state and current address space freeze freeze indicates that the cpu has entered background mode instruction pipeline pipe[1:0] indicate instruction pipeline activity master in slave out miso serial input to qspi in master mode; serial output from qspi in slave mode clock mode select modclk selects the source and type of system clock master out slave in mosi serial output from qspi in master mode; serial input to qspi in slave mode port ada pada[7:0] adc digital input port signals port c pc[6:0] sim digital output port signals port e pe[7:0] sim digital i/o port signals port f pf[7:0] sim digital i/o port signals port gp pgp[7:0] gpt digital i/o port signals port qs pqs[7:0] qsm digital i/o port signals quotient out quot provides the quotient bit of the polynomial divider read/write r/w indicates the direction of data transfer on the bus sci receive data rxd serial input to the sci qspi serial clock sck clock output from qspi in master mode; clock input to qspi in slave mode size siz[1:0] indicates the number of bytes to be transferred during a bus cycle table 6 MC68HC16Z1 signal function (continued) signal name mnemonic function .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 13 1.4 internal register address map in the following figure, imb addr[23:20] are represented by the letter y. the value represented by y determines the base address of mcu module control registers. in the MC68HC16Z1, y is equal to m111, where m is the logic state of the module mapping (mm) bit in the system integration module con- figuration register (simcr). since the cpu16 uses only addr[19:0], and addr[23:20] follow the logic state of addr19 when cpu driven, the cpu cannot access imb addresses from $080000 to $f7ffff. in order for the mcu to function correctly, mm must be set (y must equal $f). if m is cleared, internal registers are mapped to base address $700000, and are inaccessible until a reset occurs. the sram array is positioned by a base address register in the sram ctrl block. unimplemented blocks are mapped externally. figure 4 internal register addresses slave select ss causes serial transmission when qspi is in slave mode; causes mode fault in master mode three-state control tsc places all output drivers in a high-impedance state sci transmit data txd serial output from the sci adc reference voltage v rh,vrl provide precise reference for a/d conversion external filter capacitor xfc connection for external phase-locked loop filter capacitor table 6 MC68HC16Z1 signal function (continued) signal name mnemonic function z1 address map adc 64 bytes gpt 64 bytes sim 128 bytes sram ctrl 8 bytes qsm 512 bytes $yffdff $yffc00 $yffb07 $yffb00 $yffa7f $yffa00 $yff93f $yff900 $yff73f $yff700 1k sram array (mapped to 1k boundary) .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 14 MC68HC16Z1ts/d 1.5 pseudolinear memory maps the following figures both show the complete cpu16 pseudolinear address space. address space can be split into physically distinct program and data spaces by decoding the mcu function code outputs. the first figure shows the memory map of a system that has combined program and data spaces. the second figure shows the memory map when mcu function code outputs are decoded. reset and ex- ception vectors are mapped into bank 0 and cannot be relocated. the cpu16 program counter, stack pointer, and z index register can be initialized to any address in pseudolinear memory, but exception vectors are limited to 16-bit addresses ?to access locations outside of bank 0 during exception handler routines (including interrupt exceptions), a jump table must be used. figure 5 pseudolinear addressing with combined program and data spaces reset and exception vectors $ff700 $ff73f $ff900 $ff93f $ffa00 $ffa7f sim $ffb00 $ffb07 $ffc00 $ffdff adc gpt sram (control) qsm $00000 $fffff 1 mbyte reset ?initial zk, sk, and pk reset ?initial pc reset ?initial sp reset ?initial iz (direct page) bkpt (breakpoint) berr (bus error) swi (software interrupt) illegal instruction division by zero unassigned, reserved uninitialized interrupt unassigned, reserved level 1 interrupt autovector level 2 interrupt autovector level 3 interrupt autovector level 4 interrupt autovector level 5 interrupt autovector level 6 interrupt autovector level 7 interrupt autovector spurious interrupt unassigned, reserved user-defined interrupts 0000 0002 0004 0006 0008 000a 000c 000e 0010 0012?01c 001e 0020 0022 0024 0026 0028 002a 002c 002e 0030 0032?06e 0070?1fe vector address 0 4 5 6 7 8 9? f 10 11 12 13 14 15 16 17 18 19?7 38?f vector number type of exception $001fe $00000 internal registers bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 bank 9 bank 10 bank 11 bank 12 bank 13 bank 14 bank 15 $20000 $30000 $40000 $50000 $60000 $70000 $80000 $90000 $a0000 $b0000 $c0000 $d0000 $e0000 $f0000 $10000 program and data space bank 0 z1 mem map (combined) .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 15 figure 6 pseudolinear addressing with separated program and data spaces 1.6 intermodule bus the intermodule bus (imb) is a standardized bus developed to facilitate both design and operation of modular microcontrollers. it contains circuitry to support exception processing, address space partition- ing, multiple interrupt levels, and vectored interrupts. the standardized modules in the MC68HC16Z1 communicate with one another and with external components via the imb. although the full imb sup- ports 24 address and 16 data lines, the MC68HC16Z1 uses only 16 data lines and 20 address lines. because the cpu16 uses only 20 address lines, addr[23:20] are tied to addr19 when processor driven. addr[23:20] are brought out to pins for test purposes. reset ?initial zk, sk, and pk reset ?initial pc reset ?initial sp reset ?initial iz (direct page) bkpt (breakpoint) berr (bus error) swi (software interrupt) illegal instruction division by zero unassigned, reserved uninitialized interrupt unassigned, reserved level 1 interrupt autovector level 2 interrupt autovector level 3 interrupt autovector level 4 interrupt autovector level 5 interrupt autovector level 6 interrupt autovector level 7 interrupt autovector spurious interrupt unassigned, reserved user-defined interrupts 0000 0002 0004 0006 0008 000a 000c 000e 0010 0012?01c 001e 0020 0022 0024 0026 0028 002a 002c 002e 0030 0032?06e 0070?1fe vector address 0 4 5 6 7 8 9? f 10 11 12 13 14 15 16 17 18 19?7 38?f vector number type of exception $ff700 $ff73f $ff900 $ff93f $ffa00 $ffa7f sim $ffb00 $ffb07 $ffc00 $ffdff adc gpt sram (control) qsm z1 mem map (separated) $00000 $fffff $20000 $30000 $40000 $50000 $60000 $70000 $80000 $90000 $a0000 $b0000 $c0000 $d0000 $e0000 $f0000 $10000 internal registers bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 bank 9 bank 10 bank 11 bank 12 bank 13 bank 14 bank 15 bank 0 exception vectors vector address vector number type of exception 1 2 3 data space $00000 $001fe $00006 $00008 reset vectors $00000 $fffff $20000 $30000 $40000 $50000 $60000 $70000 $80000 $90000 $a0000 $b0000 $c0000 $d0000 $e0000 $f0000 $10000 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 9 bank 10 bank 11 bank 12 bank 13 bank 14 bank 15 bank 0 program space bank 8 1 mbyte $00008 $00008 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 16 MC68HC16Z1ts/d 2 cpu16 the cpu16 is a true 16-bit, high-speed device. it was designed to give m68hc11 users a path to higher performance while maintaining maximum compatibility with existing systems. 2.1 overview ease of programming is an important consideration when using a microcontroller. the cpu16 instruc- tion set is optimized for high performance. there are two 16-bit general-purpose accumulators and three 16-bit index registers. the cpu16 supports 8-bit (byte), 16-bit (word), and 32-bit (long-word) load and store operations, as well as 16- and 32-bit signed fractional operations. code development is sim- plified by the background debugging mode. cpu16 memory space includes a 1 mbyte data space and a 1 mbyte program space. twenty-bit ad- dressing and transparent bank switching are used to implement extended memory. in addition, most instructions automatically handle bank boundaries. the cpu16 includes instructions and hardware to implement control-oriented digital signal processing functions with a minimum of interfacing. a multiply and accumulate unit provides the capability to mul- tiply signed 16-bit fractional numbers and store the resulting 32-bit fixed point product in a 36-bit accu- mulator. modulo addressing supports finite impulse response filters. use of high-level languages is increasing as controller applications become more complex and control programs become larger. these languages make rapid development of portable software possible. the cpu16 instruction set supports high-level languages. 2.2 m68hc11 compatibility cpu16 architecture is a superset of m68hc11 cpu architecture. all m68hc11 cpu resources are available in the cpu16. m68hc11 cpu instructions are either directly implemented in the cpu16, or have been replaced by instructions with an equivalent form. the instruction sets are source code com- patible, but some instructions are executed differently in the cpu16. these instructions are mainly re- lated to interrupt and exception processing ?m68hc11 cpu code that processes interrupts, handles stack frames, or manipulates the condition code register must be rewritten. cpu16 execution times and number of cycles for all instructions are different from those of the m68hc11 cpu. as a result, cycle-related delays and timed control routines may be affected. the cpu16 also has several new or enhanced addressing modes. m68hc11 cpu direct mode ad- dressing has been replaced by a special form of indexed addressing that uses the new iz register and a reset vector to provide greater flexibility. .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 17 2.3 programmer's model accumulator a ?8-bit general-purpose register accumulator b ?8-bit general-purpose register accumulator d ?16-bit register formed by concatenating accumulators a and b accumulator e ?16-bit general-purpose register index register x ?16-bit indexing register, addressing extended by xk field in k register index register y ?16-bit indexing register, addressing extended by yk field in k register index register z ?16-bit indexing register, addressing extended by zk field in k register stack pointer ?16-bit dedicated register, addressing extended by the sk register program counter ?16-bit dedicated register, addressing extended by pk field in ccr condition code register ?16-bit register containing condition flags, interrupt priority mask, and the program counter address extension field k register ?16-bit register made up of four 4-bit address extension fields sk register ?4-bit register containing the stack pointer address extension field h register ?16-bit multiply and accumulate input (multiplier) register i register ?16-bit multiply and accumulate input (multiplicand) register mac accumulator ?36-bit multiply and accumulate result register xmsk, ymsk ?determine which bits change when an offset is added 20 16 15 8 7 0 a b accumulators a and b d accumulator d (a : b) e accumulator e xk ix index register x yk iy index register y zk iz index register z sk sp stack pointer pk pc program counter ccr pk condition code register pc extension register ek xk yk zk address extension register sk stack extension register h mac multiplier register i mac multiplicand register 35 16 am (msb) mac accumulatormsb [35:16] am (lsb) mac accumulator lsb [15:0] xmsk ymsk mac xy mask register .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 18 MC68HC16Z1ts/d 2.3.1 condition code register the condition code register can be considered as two functional blocks. the msb, which corresponds to the ccr in the m68hc11, contains the low-power stop control bit and processor status flags. the lsb contains the interrupt priority field, the dsp saturation mode control bit, and the program counter address extension field. s ?stop enable 0 = stop clock when lpstop instruction is executed 1 = perform nop when lpstop instruction is executed mv ?accumulator m overflow flag set when overflow into the accumulator m sign bit (am35) has occurred h ?half carry flag set when a carry from bit 3 in accumulators a or b occurs during bcd addition ev ?extension bit overflow flag set when an overflow into bit 31 of accumulator m has occurred n ?negative flag set when the msb of a result register is set z ?zero flag set when all bits of a result register are zero v ?overflow flag set when two's complement overflow occurs as the result of an operation c ?carry flag set when a carry or borrow occurs during arithmetic operation. also used during shift and rotate oper- ations to facilitate multiple word operations. int[2:0] ?interrupt priority mask the value of this field ($0 to $7) specifies the cpu16 interrupt priority level. sm ?saturate mode bit when sm is set, if either ev or mv is set, data read from accumulator m using tmrt or tmet is given maximum positive or negative value, depending on the state of the am sign bit before overflow. pk[3:0] ?program counter address extension field this field is concatenated with the program counter to form a 20-bit pseudolinear address. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s mv h ev n z v c int sm pk .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 19 2.4 data types the cpu16 supports the following data types: ? bit data ? 8-bit (byte) and 16-bit (word) integers ? 32-bit long integers ? 16-bit and 32-bit signed fractions (mac operations only) ? 20-bit effective address consisting of 16-bit page address plus 4-bit extension a byte is 8 bits wide and can be accessed at any byte location. a word is composed of two consecutive bytes, and is addressed at the lower byte. instruction fetches are always accessed on word boundaries. word operands are normally accessed on word boundaries as well, but can be accessed on odd byte boundaries, with a substantial performance penalty. to be compatible with the m68hc11, misaligned word transfers and misaligned stack accesses are al- lowed. transferring a misaligned word requires two successive byte operations. 2.5 addressing modes the cpu16 provides 10 types of addressing. each type encompasses one or more addressing modes. six cpu16 addressing types are identical to m68hc11 addressing types. all modes generate addr[15:0]. this address is combined with addr[19:16] from an extension field to form a 20-bit effective address. extension fields are part of a bank switching scheme that provides the cpu16 with a 1 mbyte address space. bank switching is transparent to most instructions ?ad- dr[19:16] of the effective address change when an access crosses a bank boundary. however, it is important to note that the value of the associated extension field is dependent on the type of instruction, and usually does not change as a result of effective address calculation. in the immediate modes, the instruction argument is contained in bytes or words immediately following the instruction. the effective address is the address of the byte following the instruction. the ais, aix/ y/z, addd and adde instructions have an extended 8-bit mode where the immediate value is an 8-bit signed number that is sign-extended to 16 bits, and then added to the appropriate register. use of the extended 8-bit mode decreases execution time. extended mode instructions contain addr[15:0] in the word following the opcode. the effective ad- dress is formed by concatenating ek and the 16-bit extension. in the indexed modes, registers ix, iy, and iz, together with their associated extension fields, are used to calculate the effective address. signed 16-bit mode and signed 20-bit mode are extensions to the m68hc11 indexed addressing mode. for 8-bit indexed mode, an 8-bit unsigned offset contained in the instruction is added to the value contained in the index register and its associated extension field. for 16-bit mode, a 16-bit signed offset contained in the instruction is added to the value contained in the index register and its associated extension field. for 20-bit mode, a 20-bit signed offset is added to the value contained in the index register. this mode is used for jmp and jsr instructions. inherent mode instructions use information available to the processor to determine the effective ad- dress. operands (if any) are system resources and are thus not fetched from memory. accumulator offset mode adds the contents of 16-bit accumulator e to one of the index registers and its associated extension field to form the effective address. this mode allows use of index registers and an accumulator within loops without corrupting accumulator d. .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 20 MC68HC16Z1ts/d relative modes are used for branch and long branch instructions. a byte or word signed two's comple- ment offset is added to the program counter if the branch condition is satisfied. the new pc value, con- catenated with the pk field, is the effective address. post-modified index mode is used with the movb and movw instructions. a signed 8-bit offset is add- ed to index register x after the effective address formed by xk and ix is used. in m68hc11 systems, direct mode can be used to perform rapid accesses to ram or i/o mapped into page 0 ($0000 to $00ff), but the cpu16 uses the first 512 bytes of page 0 for exception vectors. to compensate for the loss of direct mode, the zk field and index register z have been assigned reset ini- tialization vectors. by resetting the zk field to a chosen page, and using 8-bit unsigned index mode with iz, a programmer can access useful data structures anywhere in the address map. 2.6 instruction set the cpu16 has an 8-bit instruction set. it uses a prebyte to support a multipage opcode map. this ar- rangement makes it possible to fetch an 8-bit operand simultaneously with a page 0 opcode. if a pro- gram makes maximum use of 8-bit offset indexed addressing mode, it will have a significantly smaller instruction space. the instruction set is based on that of the m68hc11, but the opcode map has been rearranged to max- imize performance with a 16-bit data bus. all m68hc11 instructions are supported by the cpu16, al- though they may be executed differently. most m68hc11 code runs on the cpu16 following reassembly. however, take into account changed instruction times, the interrupt mask, and the new in- terrupt stack frame. the cpu16 has a full range of 16-bit arithmetic and logic instructions, including signed and unsigned multiplication and division. new instructions have been added to support extended addressing and dig- ital signal processing. the following table is a summary of the cpu16 instruction set. because it is only affected by a few in- structions, the lsb of the condition code register is not shown in the table ?instructions that affect the interrupt mask and pk field are noted. .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 21 table 7 instruction set summary mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c aba add b to a (a ) + (b) t a inh 370b 2 d d d d d abx add b to x (xk : ix) + (000 : b) t xk : ix inh 374f 2 aby add b to y (yk : iy) + (000 : b) t yk : iy inh 375f 2 abz add b to z (zk : iz) + (000 : b) t zk : iz inh 376f 2 ace add e to am[31:15] (am[31:15]) + (e) t am inh 3722 2 d d aced add concatenated e and d to am (e : d) + (am) t am inh 3723 4 d d adca add with carry to a (a) + (m) + c t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 43 53 63 73 1743 1753 1763 1773 2743 2753 2763 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d d adcb add with carry to b (b) + (m) + c t b ind8, x ind8, y ind8, z imm8 e, x e, y e, z ind16, x ind16, y ind16, z ext c3 d3 e3 f3 27c3 27d3 27e3 17c3 17d3 17e3 17f3 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d d adcd add with carry to d (d) + (m : m + 1) + c t d ind8, x ind8, y ind8, z e, x e, y e, z imm16 ind16, x ind16, y ind16, z ext 83 93 a3 2783 2793 27a3 37b3 37c3 37d3 37e3 37f3 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 6 6 6 4 6 6 6 6 d d d d adce add with carry to e (e) + (m : m + 1) + c t e imm16 ind16, x ind16, y ind16, z ext 3733 3743 3753 3763 3773 jj kk gggg gggg gggg hh ll 4 6 6 6 6 d d d d adda add to a (a) + (m) t a ind8, x ind8, y ind8, z imm8 e, x e, y e, z ind16, x ind16, y ind16, z ext 41 51 61 71 2741 2751 2761 1741 1751 1761 1771 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d d .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 22 MC68HC16Z1ts/d addb add to b (b) + (m) t b ind8, x ind8, y ind8, z imm8 e, x e, y e, z ind16, x ind16, y ind16, z ext c1 d1 e1 f1 27c1 27d1 27e1 17c1 17d1 17e1 17f1 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d d addd add to d (d) + (m : m + 1) t d ind8, x ind8, y ind8, z imm8 e, x e, y e, z imm16 ind16, x ind16, y ind16, z ext 81 91 a1 fc 2781 2791 27a1 37b1 37c1 37d1 37e1 37f1 ff ff ff ii jjkk gggg gggg gggg hh ll 6 6 6 2 6 6 6 4 6 6 6 6 d d d d adde add to e (e) + (m : m + 1) t e imm8 imm16 ind16, x ind16, y ind16, z ext 7c 3731 3741 3751 3761 3771 ii jj kk gggg gggg gggg hh ll 2 4 6 6 6 6 d d d d ade add d to e (e) + (d) t e inh 2778 2 d d d d adx add d to x (xk : ix) + (?) t xk : ix inh 37cd 2 ady add d to y (yk : iy) + (?) t yk : iy inh 37dd 2 adz add d to z (zk : iz) + (?) t zk : iz inh 37ed 2 aex add e to x (xk : ix) + (?) t xk : ix inh 374d 2 aey add e to y (yk : iy) + (?) t yk : iy inh 375d 2 aez add e to z (zk : iz) + (?) t zk : iz inh 376d 2 ais add immediate data to sp sk : sp + ?mm t sk : sp imm8 imm16 3f 373f ii jj kk 2 4 aix add immediate value to x xk : ix + ?mm t xk : ix imm8 imm16 3c 373c ii jj kk 2 4 d aiy add immediate value to y yk : iy + ?mm t yk : iy imm8 imm16 3d 373d ii jj kk 2 4 d aiz add immediate value to z zk : iz + ?mm t zk : iz imm8 imm16 3e 373e ii jj kk 2 4 d anda and a (a) ?(m) t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 46 56 66 76 1746 1756 1766 1776 2746 2756 2766 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 andb and b (b) ?(m) t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c6 d6 e6 f6 17c6 17d6 17e6 17f6 27c6 27d6 27e6 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 table 7 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 23 andd and d (d) ?(m : m + 1) t d ind8, x ind8, y ind8, z e, x e, y e, z imm16 ind16, x ind16, y ind16, z ext 86 96 a6 2786 2796 27a6 37b6 37c6 37d6 37e6 37f6 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 6 6 6 4 6 6 6 6 d d 0 ande and e (e) ?(m : m + 1) t e imm16 ind16, x ind16, y ind16, z ext 3736 3746 3756 3766 3776 jj kk gggg gggg gggg hh ll 4 6 6 6 6 d d 0 andp 1 and ccr (ccr) ?imm16 t ccr imm16 373a jj kk 4 d d d d d d d d asl arithmetic shift left ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 04 14 24 1704 1714 1724 1734 ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 d d d d asla arithmetic shift left a inh 3704 2 d d d d aslb arithmetic shift left b inh 3714 2 d d d d asld arithmetic shift left d inh 27f4 2 d d d d asle arithmetic shift left e inh 2774 2 d d d d aslm arithmetic shift left am inh 27b6 4 d d d d aslw arithmetic shift left word ind16, x ind16, y ind16, z ext 2704 2714 2724 2734 gggg gggg gggg hh ll 8 8 8 8 d d d d asr arithmetic shift right ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 0d 1d 2d 170d 171d 172d 173d ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 d d d d asra arithmetic shift right a inh 370d 2 d d d d asrb arithmetic shift right b inh 371d 2 d d d d asrd arithmetic shift right d inh 27fd 2 d d d d asre arithmetic shift right e inh 277d 2 d d d d table 7 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 24 MC68HC16Z1ts/d asrm arithmetic shift right am inh 27ba 4 d d d asrw arithmetic shift right word ind16, x ind16, y ind16, z ext 270d 271d 272d 273d gggg gggg gggg hh ll 8 8 8 8 d d d d bcc 4 branch if carry clear if c = 0, branch rel8 b4 rr 6, 2 bclr clear bit(s) (m) ?(mask ) t m ind16, x ind16, y ind16, z ext ind8, x ind8, y ind8, z 08 18 28 38 1708 1718 1728 mm gggg mm gggg mm gggg mm hh ll mm ff mm ff mm ff 8 8 8 8 8 8 8 d d 0 bclrw clear bit(s) word (m : m + 1) ?(mask ) t m : m + 1 ind16, x ind16, y ind16, z ext 2708 2718 2728 2738 gggg mmmm gggg mmmm gggg mmmm hh ll mmmm 10 10 10 10 d d 0 bcs 4 branch if carry set if c = 1, branch rel8 b5 rr 6, 2 beq 4 branch if equal if z = 1, branch rel8 b7 rr 6, 2 bge 4 branch if greater than or equal to zero if n ? v = 0, branch rel8 bc rr 6, 2 bgnd enter background de- bug mode if bdm enabled enter bdm; else, illegal instruction inh 37a6 bgt 4 branch if greater than zero if z + (n ? v) = 0, branch rel8 be rr 6, 2 bhi 4 branch if higher if c + z = 0, branch rel8 b2 rr 6, 2 bita bit test a (a) ?(m) ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 49 59 69 79 1749 1759 1769 1779 2749 2759 2769 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 bitb bit test b (b) ?(m) ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c9 d9 e9 f9 17c9 17d9 17e9 17f9 27c9 27d9 27e9 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 ble 4 branch if less than or equal to zero if z + (n ? v) = 1, branch rel8 bf rr 6, 2 bls 4 branch if lower or same if c + z = 1, branch rel8 b3 rr 6, 2 blt 4 branch if less than zero if n ? v = 1, branch rel8 bd rr 6, 2 bmi 4 branch if minus if n = 1, branch rel8 bb rr 6, 2 bne 4 branch if not equal if z = 0, branch rel8 b6 rr 6, 2 table 7 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 25 bpl 4 branch if plus if n = 0, branch rel8 ba rr 6, 2 bra branch always if 1 = 1, branch rel8 b0 rr 6 brclr 4 branch if bit(s) clear if (m) ?(mask) = 0, branch ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext cb db eb 0a 1a 2a 3a mm ff rr mm ff rr mm ff rr mm gggg rrrr mm gggg rrrr mm gggg rrrr mm hh ll rrrr 10, 12 10, 12 10, 12 10, 14 10, 14 10, 14 10, 14 brn branch never if 1 = 0, branch rel8 b1 rr 2 brset 4 branch if bit(s) set if (m ) ?(mask) = 0, branch ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 8b 9b ab 0b 1b 2b 3b mm ff rr mm ff rr mm ff rr mm gggg rrrr mm gggg rrrr mm gggg rrrr mm hh ll rrrr 10, 12 10, 12 10, 12 10, 14 10, 14 10, 14 10, 14 bset set bit(s) (m) ?(mask) t m ind16, x ind16, y ind16, z ext ind8, x ind8, y ind8, z 09 19 29 39 1709 1719 1729 mm gggg mm gggg mm gggg mm hh ll mm ff mm ff mm ff 8 8 8 8 8 8 8 d d 0 bsetw set bit(s) in word (m : m + 1) ?(mask) t m : m + 1 ind16, x ind16, y ind16, z ext 2709 2719 2729 2739 gggg mmmm gggg mmmm gggg mmmm hh ll mmmm 10 10 10 10 d d 0 bsr branch to subroutine (pk : pc) - 2 t pk : pc push (pc) (sk : sp) ?2 t sk : sp push (ccr) (sk : sp) ?2 t sk : sp (pk:pc) + offset t pk:pc rel8 36 rr 10 bvc 4 branch if overflow clear if v = 0, branch rel8 b8 rr 6, 2 bvs 4 branch if overflow set if v = 1, branch rel8 b9 rr 6, 2 cba compare a to b (a) ?(b) inh 371b 2 d d d d clr clear memory $00 t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 05 15 25 1705 1715 1725 1735 ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 0 1 0 0 clra clear a $00 t a inh 3705 2 0 1 0 0 clrb clear b $00 t b inh 3715 2 0 1 0 0 clrd clear d $0000 t d inh 27f5 2 0 1 0 0 clre clear e $0000 t e inh 2775 2 0 1 0 0 clrm clear am $000000000 t am[32:0] inh 27b7 2 0 0 table 7 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 26 MC68HC16Z1ts/d clrw clear memory word $0000 t m : m + 1 ind16, x ind16, y ind16, z ext 2705 2715 2725 2735 gggg gggg gggg hh ll 6 6 6 6 0 1 0 0 cmpa compare a to memory (a) ?(m) ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 48 58 68 78 1748 1758 1768 1778 2748 2758 2768 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d cmpb compare b to memory (b) ?(m) ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c8 d8 e8 f8 17c8 17d8 17e8 17f8 27c8 27d8 27e8 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d com one? complement $ff ?(m) t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 00 10 20 1700 1710 1720 1730 ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 d d 0 1 coma one? complement a $ff ?(a) t a inh 3700 2 d d 0 1 comb one? complement b $ff ?(b) t b inh 3710 2 d d 0 1 comd one? complement d $ffff ?(d) t d inh 27f0 2 d d 0 1 come one? complement e $ffff ?(e) t e inh 2770 2 d d 0 1 comw one? complement word $ffff ?m : m + 1 t m : m + 1 ind16, x ind16, y ind16, z ext 2700 2710 2720 2730 gggg gggg gggg hh ll 8 8 8 8 d d 0 1 cpd compare d to memory (d) ?(m : m + 1) ind8, x ind8, y ind8, z e, x e, y e, z imm16 ind16, x ind16, y ind16, z ext 88 98 a8 2788 2798 27a8 37b8 37c8 37d8 37e8 37f8 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 6 6 6 4 6 6 6 6 d d d d cpe compare e to memory (e) ?(m : m + 1) imm16 ind16, x ind16, y ind16, z ext 3738 3748 3758 3768 3778 jjkk gggg gggg gggg hhll 4 6 6 6 6 d d d d cps compare sp to memory (sp) ?(m : m + 1) ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext imm16 4f 5f 6f 174f 175f 176f 177f 377f ff ff ff gggg gggg gggg hh ll jj kk 6 6 6 6 6 6 6 4 d d d d table 7 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 27 cpx compare ix to memory (ix) ?(m : m + 1) ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext imm16 4c 5c 6c 174c 175c 176c 177c 377c ff ff ff gggg gggg gggg hh ll jj kk 6 6 6 6 6 6 6 4 d d d d cpy compare iy to memory (iy) ?(m : m + 1) ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext imm16 4d 5d 6d 174d 175d 176d 177d 377d ff ff ff gggg gggg gggg hh ll jj kk 6 6 6 6 6 6 6 4 d d d d cpz compare iz to memory (iz) ?(m : m + 1) ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext imm16 4e 5e 6e 174e 175e 176e 177e 377e ff ff ff gggg gggg gggg hh ll jj kk 6 6 6 6 6 6 6 4 d d d d daa decimal adjust a (a) 10 inh 3721 2 d d u d dec decrement memory (m) ?$01 t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 01 11 21 1701 1711 1721 1731 ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 d d d deca decrement a (a) ?$01 t a inh 3701 2 d d d decb decrement b (b) ?$01 t b inh 3711 2 d d d decw decrement memory word (m : m + 1) ?$0001 t m : m + 1 ind16, x ind16, y ind16, z ext 2701 2711 2721 2731 gggg gggg gggg hh ll 8 8 8 8 d d d ediv extended unsigned divide (e : d) / (ix) quotient t ix remainder t d inh 3728 24 d d d d edivs extended signed di- vide (e : d) / (ix) quotient t ix remainder t accd inh 3729 38 d d d d emul extended unsigned multiply (e) * (d) t e : d inh 3725 10 d d d emuls extended signed mul- tiply (e) * (d) t e : d inh 3726 8 d d d eora exclusive or a (a) ? (m) t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 44 54 64 74 1744 1754 1764 1774 2744 2754 2764 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 table 7 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 28 MC68HC16Z1ts/d eorb exclusive or b (b) ? (m) t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c4 d4 e4 f4 17c4 17d4 17e4 17f4 27c4 27d4 27e4 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 eord exclusive or d (d) ? (m : m + 1) t d ind8, x ind8, y ind8, z e, x e, y e, z imm16 ind16, x ind16, y ind16, z ext 84 94 a4 2784 2794 27a4 37b4 37c4 37d4 37e4 37f4 ff ff ff jjkk gggg gggg gggg hhll 6 6 6 6 6 6 4 6 6 6 6 d d 0 eore exclusive or e (e) ? (m : m + 1) t e imm16 ind16, x ind16, y ind16, z ext 3734 3744 3754 3764 3774 jj kk gggg gggg gggg hh ll 4 6 6 6 6 d d 0 fdiv fractional unsigned divide (d) / (ix) t ix remainder t d inh 372b 22 d d d fmuls fractional signed multiply (e) * (d) t e : d[31:1] 0 t d[0] inh 3727 8 d d d d idiv integer divide (d) / (ix) t ix; remainder t d inh 372a 22 d 0 d inc increment memory (m) + $01 t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 03 13 23 1703 1713 1723 1733 ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 d d d inca increment a (a) + $01 t a inh 3703 2 d d d incb increment b (b) + $01 t b inh 3713 2 d d d incw increment memory word (m : m + 1) + $0001 t m : m + 1 ind16, x ind16, y ind16, z ext 2703 2713 2723 2733 gggg gggg gggg hh ll 8 8 8 8 d d d jmp jump ea ? t pk : pc ind20, x ind20, y ind20, z ext20 4b 5b 6b 7a zg gggg zg gggg zg gggg zb hh ll 8 8 8 6 jsr jump to subroutine push (pc) (sk : sp) ?2 t sk : sp push (ccr) (sk : sp) ?2 t sk : sp ea ? t pk : pc ind20, x ind20, y ind20, z ext20 89 99 a9 fa zg gggg zg gggg zg gggg zb hh ll 12 12 12 10 lbcc 4 long branch if carry clear if c = 0, branch rel16 3784 rrrr 6, 4 lbcs 4 long branch if carry set if c = 1, branch rel16 3785 rrrr 6, 4 lbeq 4 long branch if equal if z = 1, branch rel16 3787 rrrr 6, 4 lbev 4 long branch if ev set if ev = 1, branch rel16 3791 rrrr 6, 4 lbge 4 long branch if greater than or equal to zero if n ? v = 0, branch rel16 378c rrrr 6, 4 lbgt 4 long branch if greater than zero if z ; (n ? v) = 0, branch rel16 378e rrrr 6, 4 table 7 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 29 lbhi 4 long branch if higher if c ; z = 0, branch rel16 3782 rrrr 6, 4 lble 4 long branch if less than or equal to zero if z ; (n ? v) = 1, branch rel16 378f rrrr 6, 4 lbls 4 long branch if lower or same if c ; z = 1, branch rel16 3783 rrrr 6, 4 lblt 4 long branch if less than zero if n ? v = 1, branch rel16 378d rrrr 6, 4 lbmi 4 long branch if minus if n = 1, branch rel16 378b rrrr 6, 4 lbmv 4 long branch if mv set if mv = 1, branch rel16 3790 rrrr 6, 4 lbne 4 long branch if not equal if z = 0, branch rel16 3786 rrrr 6, 4 lbpl 4 long branch if plus if n = 0, branch rel16 378a rrrr 6, 4 lbra long branch always if 1 = 1, branch rel16 3780 rrrr 6 lbrn long branch never if 1 = 0, branch rel16 3781 rrrr 6 lbsr long branch to subroutine push (pc) (sk : sp) ?2 t sk : sp push (ccr) (sk : sp) ?2 t sk : sp (pk : pc) + offset t pk : pc rel16 27f9 rrrr 10 lbvc 4 long branch if overflow clear if v = 0, branch rel16 3788 rrrr 6, 4 lbvs 4 long branch if overflow set if v = 1, branch rel16 3789 rrrr 6, 4 ldaa load a (m) t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 45 55 65 75 1745 1755 1765 1775 2745 2755 2765 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 ldab load b (m) t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c5 d5 e5 f5 17c5 17d5 17e5 17f5 27c5 27d5 27e5 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 ldd load d (m : m + 1) t d ind8, x ind8, y ind8, z e, x e, y e, z imm16 ind16, x ind16, y ind16, z ext 85 95 a5 2785 2795 27a5 37b5 37c5 37d5 37e5 37f5 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 6 6 6 4 6 6 6 6 d d 0 lde load e (m : m + 1) t e imm16 ind16, x ind16, y ind16, z ext 3735 3745 3755 3765 3775 jj kk gggg gggg gggg hh ll 4 6 6 6 6 d d 0 lded load concatenated e and d (m : m + 1) t e (m + 2 : m + 3) t d ext 2771 hh ll 8 table 7 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 30 MC68HC16Z1ts/d ldhi initialize h and i (m : m + 1) x t h r (m : m + 1) y t i r ext 27b0 8 lds load sp (m : m + 1) t sp ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext imm16 cf df ef 17cf 17df 17ef 17ff 37bf ff ff ff gggg gggg gggg hh ll jj kk 6 6 6 6 6 6 6 4 d d 0 ldx load ix (m : m + 1) t ix ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext imm16 cc dc ec 17cc 17dc 17ec 17fc 37bc ff ff ff gggg gggg gggg hh ll jj kk 6 6 6 6 6 6 6 4 d d 0 ldy load iy (m : m + 1) t iy ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext imm16 cd dd ed 17cd 17dd 17ed 17fd 37bd ff ff ff gggg gggg gggg hh ll jj kk 6 6 6 6 6 6 6 4 d d 0 ldz load iz (m : m + 1) t iz ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext imm16 ce de ee 17ce 17de 17ee 17fe 37be ff ff ff gggg gggg gggg hh ll jj kk 6 6 6 6 6 6 6 4 d d 0 lpstop low power stop if s then stop else nop inh 27f1 4, 20 lsr logical shift right ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 0f 1f 2f 170f 171f 172f 173f ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 0 d d d lsra logical shift right a inh 370f 2 0 d d d lsrb logical shift right b inh 371f 2 0 d d d lsrd logical shift right d inh 27ff 2 0 d d d lsre logical shift right e inh 277f 2 0 d d d lsrw logical shift right word ind16, x ind16, y ind16, z ext 270f 271f 272f 273f gggg gggg gggg hh ll 8 8 8 8 0 d d d table 7 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 31 mac multiply and accumulate signed 16-bit fractions (hr) * (ir) t e : d (am) + (e : d) t am qualified (ix) t ix qualified (iy) t iy (hr) t iz (m : m + 1) x t hr (m : m + 1) y t ir imm8 7b xoyo 12 d d d movb move byte (m 1 ) t m 2 ixp to ext ext to ixp ext to ext 30 32 37fe ff hh ll ff hh ll hh ll hh ll 8 8 10 d d 0 movw move word (m : m + 1 1 ) t m : m + 1 2 ixp to ext ext to ixp ext to ext 31 33 37ff ff hh ll ff hh ll hh ll hh ll 8 8 10 d d 0 mul multiply (a) * (b) t d inh 3724 10 d neg negate memory $00 ?(m) t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 02 12 22 1702 1712 1722 1732 ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 d d d d nega negate a $00 ?(a) t a inh 3702 2 d d d d negb negate b $00 ?(b) t b inh 3712 2 d d d d negd negate d $0000 ?(d) t d inh 27f2 2 d d d d nege negate e $0000 ?(e) t e inh 2772 2 d d d d negw negate memory word $0000 ?(m : m + 1) t m : m + 1 ind16, x ind16, y ind16, z ext 2702 2712 2722 2732 gggg gggg gggg hh ll 8 8 8 8 d d d d nop null operation inh 274c 2 oraa or a (a) ; (m) t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 47 57 67 77 1747 1757 1767 1777 2747 2757 2767 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 orab or b (b) ; (m) t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c7 d7 e7 f7 17c7 17d7 17e7 17f7 27c7 27d7 27e7 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 ord or d (d) ; (m : m + 1) t d ind8, x ind8, y ind8, z e, x e, y e, z imm16 ind16, x ind16, y ind16, z ext 87 97 a7 2787 2797 27a7 37b7 37c7 37d7 37e7 37f7 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 6 6 6 4 6 6 6 6 d d 0 table 7 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 32 MC68HC16Z1ts/d ore or e (e) ; (m : m + 1) t e imm16 ind16, x ind16, y ind16, z ext 3737 3747 3757 3767 3777 jj kk gggg gggg gggg hh ll 4 6 6 6 6 d d 0 orp 1 or condition code register (ccr) ; imm16 t ccr imm16 373b jj kk 4 d d d d d d d d psha push a (sk : sp) + 1 t sk : sp push (a) (sk : sp) ?2 t sk : sp inh 3708 4 pshb push b (sk : sp) + 1 t sk : sp push (b) (sk : sp) ?2 t sk : sp inh 3718 4 pshm push multiple registers mask bits: 0 = d 1 = e 2 = ix 3 = iy 4 = iz 5 = k 6 = ccr 7 = (reserved) for mask bits 0 to 7: if mask bit set push register (sk : sp) ?2 t sk : sp imm8 34 ii 4 + 2n n = number of iterations pshmac push mac state mac registers t stack inh 27b8 14 pula pull a (sk : sp) + 2 t sk : sp pull (a) (sk : sp) ?1 t sk : sp inh 3709 6 pulb pull b (sk : sp) + 2 t sk : sp pull (b) (sk : sp) ?1 t sk : sp inh 3719 6 pulm 1 pull multiple registers mask bits: 0 = ccr[15:4] 1 = k 2 = iz 3 = iy 4 = ix 5 = e 6 = d 7 = (reserved) for mask bits 0 to 7: if mask bit set (sk : sp) + 2 t sk : sp pull register imm8 35 ii 4+2(n+1) n = number of iterations d d d d d d d d pulmac pull mac state stack t mac registers inh 27b9 16 rmac repeating multiply and accumulate signed 16-bit fractions repeat until (e) < 0 (am) + (h) * (i) t am qualified (ix) t ix; qualified (iy) t iy; (m : m + 1) x t h; (m : m + 1) y t i (e) ?1 t e imm8 fb xoyo 6 + 12 per iteration d d rol rotate left ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 0c 1c 2c 170c 171c 172c 173c ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 d d d d rola rotate left a inh 370c 2 d d d d rolb rotate left b inh 371c 2 d d d d table 7 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 33 rold rotate left d inh 27fc 2 d d d d role rotate left e inh 277c 2 d d d d rolw rotate left word ind16, x ind16, y ind16, z ext 270c 271c 272c 273c gggg gggg gggg hh ll 8 8 8 8 d d d d ror rotate right ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 0e 1e 2e 170e 171e 172e 173e ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 d d d d rora rotate right a inh 370e 2 d d d d rorb rotate right b inh 371e 2 d d d d rord rotate right d inh 27fe 2 d d d d rore rotate right e inh 277e 2 d d d d rorw rotate right word ind16, x ind16, y ind16, z ext 270e 271e 272e 273e gggg gggg gggg hh ll 8 8 8 8 d d d d rti 2 return from interrupt (sk : sp) + 2 t sk : sp pull ccr (sk : sp) + 2 t sk : sp pull pc (pk : pc) ?6 t pk : pc inh 2777 12 d d d d d d d d rts 3 return from subrou- tine (sk : sp) + 2 t sk : sp pull pk (sk : sp) + 2 t sk : sp pull pc (pk : pc) ?2 t pk : pc inh 27f7 12 sba subtract b from a (a) ?(b) t a inh 370a 2 d d d d sbca subtract with carry from a (a) ?(m) ?c t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 42 52 62 72 1742 1752 1762 1772 2742 2752 2762 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d table 7 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 34 MC68HC16Z1ts/d sbcb subtract with carry from b (b) ?(m) ?c t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c2 d2 e2 f2 17c2 17d2 17e2 17f2 27c2 27d2 27e2 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d sbcd subtract with carry from d (d) ?(m : m + 1) ?c t d ind8, x ind8, y ind8, z e, x e, y e, z imm16 ind16, x ind16, y ind16, z ext 82 92 a2 2782 2792 27a2 37b2 37c2 37d2 37e2 37f2 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 6 6 6 4 6 6 6 6 d d d d sbce subtract with carry from e (e) ?(m : m + 1) ?c t e imm16 ind16, x ind16, y ind16, z ext 3732 3742 3752 3762 3772 jj kk gggg gggg gggg hh ll 4 6 6 6 6 d d d d sde subtract d from e (e) ?(d) t e inh 2779 2 d d d d staa store a (a) t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext e, x e, y e, z 4a 5a 6a 174a 175a 176a 177a 274a 275a 276a ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 4 4 4 d d 0 stab store b (b) t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext e, x e, y e, z ca da ea 17ca 17da 17ea 17fa 27ca 27da 27ea ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 4 4 4 d d 0 std store d (d) t m : m + 1 ind8, x ind8, y ind8, z e, x e, y e, z ind16, x ind16, y ind16, z ext 8a 9a aa 278a 279a 27aa 37ca 37da 37ea 37fa ff ff ff gggg gggg gggg hh ll 6 6 6 6 6 6 4 4 4 6 d d 0 ste store e (e) t m : m + 1 ind16, x ind16, y ind16, z ext 374a 375a 376a 377a gggg gggg gggg hh ll 6 6 6 6 d d 0 sted store concatenated d and e (e) t m : m + 1 (d) t m + 2 : m + 3 ext 2773 hh ll 8 table 7 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 35 sts store sp (sp) t m : m + 1 ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 8f 9f af 178f 179f 17af 17bf ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 d d 0 stx store ix (ix) t m : m + 1 ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 8c 9c ac 178c 179c 17ac 17bc ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 d d 0 sty store iy (iy) t m : m + 1 ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 8d 9d ad 178d 179d 17ad 17bd ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 d d 0 stz store z (iz) t m : m + 1 ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 8e 9e ae 178e 179e 17ae 17be ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 d d 0 suba subtract from a (a) ?(m) t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 40 50 60 70 1740 1750 1760 1770 2740 2750 2760 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d subb subtract from b (b) ?(m) t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c0 d0 e0 f0 17c0 17d0 17e0 17f0 27c0 27d0 27e0 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d subd subtract from d (d) ?(m : m + 1) t d ind8, x ind8, y ind8, z e, x e, y e, z imm16 ind16, x ind16, y ind16, z ext 80 90 a0 2780 2790 27a0 37b0 37c0 37d0 37e0 37f0 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 6 6 6 4 6 6 6 6 d d d d sube subtract from e (e) ?(m : m + 1) t e imm16 ind16, x ind16, y ind16, z ext 3730 3740 3750 3760 3770 jj kk gggg gggg gggg hh ll 4 6 6 6 6 d d d d table 7 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 36 MC68HC16Z1ts/d swi software interrupt (pk : pc) + 2 t pk : pc push (pc) (sk : sp) ?2 t sk : sp push (ccr) (sk : sp) ?2 t sk : sp $0 t pk swi vector t pc inh 3720 16 sxt sign extend b into a if b7 = 1 then a = $ff else a = $00 inh 27f8 2 d d tab transfer a to b (a) t b inh 3717 2 d d 0 tap transfer a to ccr (a[7:0]) t ccr[15:8] inh 37fd 4 d d d d d d d d tba transfer b to a (b) t a inh 3707 2 d d 0 tbek transfer b to ek (b) t ek inh 27fa 2 tbsk transfer b to sk (b) t sk inh 379f 2 tbxk transfer b to xk (b) t xk inh 379c 2 tbyk transfer b to yk (b) t yk inh 379d 2 tbzk transfer b to zk (b) t zk inh 379e 2 tde transfer d to e (d) t e inh 277b 2 d d 0 tdmsk transfer d to xmsk : ymsk (d[15:8]) t x mask (d[7:0]) t y mask inh 372f 2 tdp 1 transfer d to ccr (d) t ccr[15:4] inh 372d 4 d d d d d d d d ted transfer e to d (e) t d inh 27fb 2 d d 0 tedm transfer e and d to am[31:0] sign extend am (d) t am[15:0] (e) t am[31:16] am[35:32] = am31 inh 27b1 4 0 0 tekb transfer ek to b $0 t b[7:4] (ek) t b[3:0] inh 27bb 2 tem transfer e to am[31:16] sign extend am clear am lsb (e) t am[31:16] $00 t am[15:0] am[35:32] = am31 inh 27b2 4 0 0 tmer transfer am to e rounded rounded (am) t temp if (sm (ev ; mv)) then saturation t e else temp[31:16] t e inh 27b4 6 d d d d tmet transfer am to e trun- cated if (sm (ev ; mv)) then saturation t e else am[31:16] t e inh 27b5 2 d d tmxed transfer am to ix : e : d am[35:32] t ix[3:0] am35 t ix[15:4] am[31:16] t e am[15:0] t d inh 27b3 6 tpa transfer ccr msb to a (ccr[15:8]) t a inh 37fc 2 tpd transfer ccr to d (ccr) t d inh 372c 2 tskb transfer sk to b (sk) t b[3:0] $0 t b[7:4] inh 37af 2 tst test for zero or minus (m) ?$00 ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 06 16 26 1706 1716 1726 1736 ff ff ff gggg gggg gggg hh ll 6 6 6 6 6 6 6 d d 0 0 tsta test a for zero or minus (a) ?$00 inh 3706 2 d d 0 0 tstb test b for zero or minus (b) ?$00 inh 3716 2 d d 0 0 tstd test d for zero or minus (d) ?$0000 inh 27f6 2 d d 0 0 tste test e for zero or minus (e) ?$0000 inh 2776 2 d d 0 0 table 7 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 37 tstw test for zero or minus word (m : m + 1) ?$0000 ind16, x ind16, y ind16, z ext 2706 2716 2726 2736 gggg gggg gggg hh ll 6 6 6 6 d d 0 0 tsx transfer sp to x (sk : sp) + 2 t xk : ix inh 274f 2 tsy transfer sp to y (sk : sp) + 2 t yk : iy inh 275f 2 tsz transfer sp to z (sk : sp) + 2 t zk : iz inh 276f 2 txkb transfer xk to b $0 t b[7:4] (xk) t b[3:0] inh 37ac 2 txs transfer x to sp (xk : ix) ?2 t sk : sp inh 374e 2 txy transfer x to y (xk : ix) t yk : iy inh 275c 2 txz transfer x to z (xk : ix) t zk : iz inh 276c 2 tykb transfer yk to b $0 t b[7:4] (yk) t b[3:0] inh 37ad 2 tys transfer y to sp (yk : iy) ?2 t sk : sp inh 375e 2 tyx transfer y to x (yk : iy) t xk : ix inh 274d 2 tyz transfer y to z (yk : iy) t zk : iz inh 276d 2 tzkb transfer zk to b $0 t b[7:4] (zk) t b[3:0] inh 37ae 2 tzs transfer z to sp (zk : iz) ?2 t sk : sp inh 376e 2 tzx transfer z to x (zk : iz) t xk : ix inh 274e 2 tzy transfer z to y (zk : iz) t zk : iy inh 275e 2 wai wait for interrupt wait inh 27f3 8 xgab exchange a with b (a) ? (b) inh 371a 2 xgde exchange d with e (d) ? (e) inh 277a 2 xgdx exchange d with x (d) ? (ix) inh 37cc 2 xgdy exchange d with y (d) ? (iy) inh 37dc 2 xgdz exchange d with z (d) ? (iz) inh 37ec 2 xgex exchange e with x (e) ? (ix) inh 374c 2 xgey exchange e with y (e) ? (iy) inh 375c 2 xgez exchange e with z (e) ? (iz) inh 376c 2 notes: 1. ccr[15:4] change according to results of operation. the pk field is not affected. 2. ccr[15:0] change according to copy of ccr pulled from stack. 3. pk field changes according to state pulled from stack. the rest of the ccr is not affected. 4. cycle times for conditional branches are shown in "taken, not taken" order. table 7 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 38 MC68HC16Z1ts/d table 8 instruction set abbreviations and symbols a accumulator a x register used in operation am accumulator m m address of one memory byte b accumulator b m +1 address of byte at m + $0001 ccr condition code register m : m + 1 address of one memory word d accumulator d (...) x contents of address pointed to by ix e accumulator e (...) y contents of address pointed to by iy ek extended addressing extension field (...) z contents of address pointed to by iz ir mac multiplicand register e, x ix with e offset hr mac multiplier register e, y iy with e offset ix index register x e, z iz with e offset iy index register y ext extended iz index register z ext20 20-bit extended k address extension register imm8 8-bit immediate pc program counter imm16 16-bit immediate pk program counter extension field ind8, x ix with unsigned 8-bit offset sk stack pointer extension field ind8, y iy with unsigned 8-bit offset sl multiply and accumulate sign latch ind8, z iz with unsigned 8-bit offset sp ? stack pointer ind16, x ix with signed 16-bit offset xk index register x extension field ind16, y iy with signed 16-bit offset yk index register y extension field ind16, z iz with signed 16-bit offset zk index register z extension field ind20, x ix with signed 20-bit offset xmsk modulo addressing index register x mask ind20, y iy with signed 20-bit offset ymsk modulo addressing index register y mask ind20, z iz with signed 20-bit offset s stop disable control bit inh inherent mv am overflow indicator ixp post-modified indexed h half carry indicator rel8 8-bit relative ev am extended overflow indicator rel16 16-bit relative n negative indicator b 4-bit address extension z zero indicator ff 8-bit unsigned offset v two's complement overflow indicator gggg 16-bit signed offset c carry/borrow indicator hh high byte of 16-bit extended address ip interrupt priority field ii 8-bit immediate data sm saturation mode control bit jj high byte of 16-bit immediate data pk program counter extension field kk low byte of 16-bit immediate data bit not affected ll low byte of 16-bit extended address d bit changes as specified mm 8-bit mask 0 bit cleared mmmm 16-bit mask 1 bit set rr 8-bit unsigned relative offset m memory location used in operation rrrr 16-bit signed relative offset r result of operation xo mac index register x offset s source data yo mac index register y offset z 4-bit zero extension + addition and - subtraction or negation (2's complement) + inclusive or (or) multiplication ? exclusive or (eor) / division not complementation > greater : concatenation < less t transferred = equal ? exchanged 3 equal or greater sign bit; also used to show tolerance equal or less sign extension 1 not equal % binary value $ hexadecimal value .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 39 2.7 exceptions an exception is an event that preempts normal instruction process. exception processing makes the transition from normal instruction execution to execution of a routine that deals with an exception. each exception has an assigned vector that points to an associated handler routine. exception process- ing includes all operations required to transfer control to a handler routine, but does not include execu- tion of the handler routine. 2.7.1 exception vectors an exception vector is the address of a routine that handles an exception. exception vectors are con- tained in a data structure called the instruction vector table, which is located in the first 512 bytes of bank 0. all vectors, except the reset vector, consist of one word and reside in data space. the reset vector con- sists of four words that reside in program space. there are 52 predefined or reserved vectors, and 200 user-defined vectors. each vector is assigned an 8-bit number. vector numbers for some exceptions are generated by exter- nal devices; others are supplied by the processor. there is a direct mapping of vector number to vector table address. the cpu16 left shifts the vector number one place (multiplies by two) to convert it to an address. table 9 exception vector table vector number vector address address space type of exception 0 0000 p reset ?initial zk, sk, and pk 0002 p reset ?initial pc 0004 p reset ?initial sp 0006 p reset ?initial iz (direct page) 4 0008 d bkpt (breakpoint) 5 000a d berr (bus error) 6 000c d swi (software interrupt) 7 000e d illegal instruction 8 0010 d division by zero 9 ?e 0012 ?001c d unassigned, reserved f 001e d uninitialized interrupt 10 0020 d unassigned, reserved 11 0022 d level 1 interrupt autovector 12 0024 d level 2 interrupt autovector 13 0026 d level 3 interrupt autovector 14 0028 d level 4 interrupt autovector 15 002a d level 5 interrupt autovector 16 002c d level 6 interrupt autovector 17 002e d level 7 interrupt autovector 18 0030 d spurious interrupt 19 ?37 0032 ?006e d unassigned, reserved 38 ?ff 0070 ?01fe d user-defined interrupts .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 40 MC68HC16Z1ts/d 2.7.2 exception stack frame during exception processing, the contents of the program counter and condition code register are stacked at a location pointed to by sk : sp. unless it is altered during exception processing, the stacked pk : pc value is the address of the next instruction in the current instruction stream, plus $0006. the following figure shows the exception stack frame. figure 7 exception stack frame 2.7.3 exception processing sequence exception processing is performed in four distinct phases. ?priority of all pending exceptions is evaluated, and the highest priority exception is processed first. ?processor state is stacked, then the ccr pk extension field is cleared. ?an exception vector number is acquired and converted to a vector address. ?the content of the vector address is loaded into the pc, and the processor jumps to the exception handler routine. there are variations within each phase for differing types of exceptions. however, all vectors but reset contain 16-bit addresses, and the pk field is cleared. exception handlers must be located within bank 0, or vectors must point to a jump table. 2.7.4 types of exceptions exceptions can be generated either internally or externally. external exceptions which are defined as asynchronous, include interrupts, bus errors (berr), breakpoints (bkpt), and resets (reset). inter- nal exceptions, which are defined as synchronous, include the software interrupt (swi) instruction, the background (bgnd) instruction, illegal instruction exceptions, and the divide-by-zero exception. refer to 3 system integration module for more information about resets and interrupts. asynchronous exceptions occur without reference to cpu16 or imb clocks, but exception processing is synchronized. for all asynchronous exceptions but reset, exception processing begins at the first instruction boundary following recognition of an exception. synchronous exception processing is part of an instruction definition. exception processing for synchro- nous exceptions will always be completed, and the first instruction of the handler routine will always be executed, before interrupts are detected. because of pipelining, the stacked return pk : pc value for asynchronous exceptions, other than re- set, is equal to the address of the next instruction in the current instruction stream plus $0006. the rti instruction, which must terminate all exception handler routines, subtracts $0006 from the stacked value in order to resume execution of the interrupted instruction stream. the value of pk : pc at the time a synchronous exception executes is equal to the address of the instruction that causes the excep- tion plus $0006. since rti always subtracts $0006 upon return, the stacked pk : pc must be adjusted by the instruction that caused the exception so that execution will resume with the following instruction. $0002 is added to the pk : pc value before it is stacked. low address sp after exception stacking condition code register high address program counter sp before exception stacking .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 41 2.7.5 multiple exceptions each exception has a hardware priority based upon its relative importance to system operation. asyn- chronous exceptions have higher priorities than synchronous exceptions. exception processing for mul- tiple exceptions is done by priority, from lowest to highest. note that priority governs the order in which exception processing occurs, not the order in which exception handlers are executed. unless bus error, breakpoint, or reset occur during exception processing, the first instruction of all ex- ception handler routines is guaranteed to execute before another exception is processed. because in- terrupt exceptions have higher priority than synchronous exceptions, the first instruction in an interrupt handler is executed before other interrupts are sensed. bus error, breakpoint, and reset exceptions that occur during exception processing of a previous excep- tion are processed before the first instruction of that exception's handler routine. the converse is not true. if an interrupt occurs during berr exception processing, for example, the first instruction of the berr handler is executed before interrupts are sensed. this permits the exception handler to mask interrupts during execution. 2.7.6 rti instruction the return-from-interrupt instruction (rti) must be the last instruction in all exception handlers except for the reset handler. rti pulls the exception stack frame that was pushed onto the system stack during exception processing, and restores processor state. normal program flow resumes at the address of the instruction that follows the last instruction executed before exception processing began. rti is not used in the reset handler because a reset initializes the stack pointer and does not create a stack frame. .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 42 MC68HC16Z1ts/d 3 system integration module the MC68HC16Z1 system integration module (sim) consists of five functional blocks that control sys- tem start-up, initialization, configuration, and the external bus. figure 8 sim block diagram sim block system configuration and protection clock synthesizer chip selects external bus interface factory test clkout extal modclk chip selects external bus reset tstme freeze/quot upper address .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 43 table 10 sim address map address 15 8 7 0 yffa00 module configuration (simcr) yffa02 factory test (simtr) yffa04 clock synthesizer control (syncr) yffa06 unused reset status register (rsr) yffa08 module test e (simtre) yffa0a unused unused yffa0c unused unused yffa0e unused unused yffa10 unused porte data (porte0) yffa12 unused porte data (porte1) yffa14 unused porte data direction (ddre) yffa16 unused porte pin assignment (pepar) yffa18 unused portf data (portf0) yffa1a unused portf data (portf1) yffa1c unused portf data direction (ddrf) yffa1e unused portf pin assignment (pfpar) yffa20 unused system protection control (sypcr) yffa22 periodic interrupt control (picr) yffa24 periodic interrupt timing (pitr) yffa26 unused software service (swsr) yffa28 unused unused yffa2a unused unused yffa2c unused unused yffa2e unused unused yffa30 test module master shift a (tstmsra) yffa32 test module master shift b (tstmsrb) yffa34 test module shift count (tstsc) yffa36 test module repetition counter (tstrc) yffa38 test module control (creg) yffa3a test module distributed register (dreg) yffa3c unused unused yffa3e unused unused yffa40 unused port c data (portc) yffa42 unused unused yffa44 chip-select pin assignment (cspar0) yffa46 chip-select pin assignment (cspar1) yffa48 chip-select base boot (csbarbt) yffa4a chip-select option boot (csorbt) yffa4c chip-select base 0 (csbar0) yffa4e chip-select option 0 (csor0) yffa50 chip-select base 1 (csbar1) yffa52 chip-select option 1 (csor1) yffa54 chip-select base 2 (csbar2) yffa56 chip-select option 2 (csor2) yffa58 chip-select base 3 (csbar3) yffa5a chip-select option 3 (csor3) yffa5c chip-select base 4 (csbar4) .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 44 MC68HC16Z1ts/d y = m111 where m is the logic state of the modmap (mm) bit in the simcr yffa5e chip-select option 4 (csor4) yffa60 chip-select base 5 (csbar5) yffa62 chip-select option 5 (csor5) yffa64 chip-select base 6 (csbar6) yffa66 chip-select option 6 (csor6) yffa68 chip-select base 7 (csbar7) yffa6a chip-select option 7 (csor7) yffa6c chip-select base 8 (csbar8) yffa6e chip-select option 8 (csor8) yffa70 chip-select base 9 (csbar9) yffa72 chip-select option 9 (csor9) yffa74 chip-select base 10 (csbar10) yffa76 chip-select option 10 (csor10) yffa78 unused unused yffa7a unused unused yffa7c unused unused yffa7e unused unused table 10 sim address map address 15 8 7 0 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 45 3.1 system configuration and protection this functional block provides configuration control for the entire MC68HC16Z1. it also performs inter- rupt arbitration, bus monitoring, and system test functions. figure 9 system configuration and protection block diagram 3.2 system configuration the sim controls m68hc16 configuration during normal operation and during internal testing. mcr ?module configuration register $yffa00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 exoff frzsw frzbm 0 slven 0 shen supv mm 0 0 iarb reset: 0 0 0 0 db11 0 0 0 1 1 0 0 1 1 1 1 sys protect block module configuration and test reset status halt monitor bus monitor spurious interrupt monitor software watchdog timer periodic interrupt timer prescaler clock berr reset request reset request 2 9 irq [7:1 ] halt or software or .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 46 MC68HC16Z1ts/d the module configuration register controls system configuration. it can be read or written at any time, except for the module mapping (mm) bit, which can be written once and must remain set. exoff ?external clock off 0 = the clkout pin is driven from an internal clock source. 1 = the clkout pin is placed in a high-impedance state. frzsw ?freeze software enable 0 = when freeze is asserted, the software watchdog and periodic interrupt timer counters con- tinue to run. 1 = when freeze is asserted, the software watchdog and periodic interrupt timer counters are dis- abled, preventing interrupts during software debug. frzbm ?freeze bus monitor enable 0 = when freeze is asserted, the bus monitor continues to operate. 1 = when freeze is asserted, the bus monitor is disabled. slven ?factory test mode enabled this bit is a read-only status bit that reflects the state of db11 during reset. 0 = imb is not available to an external master. 1 = an external bus master has direct access to the imb. shen[1:0] ?show cycle enable this field determines what the ebi does with the external bus during internal transfer operations. a show cycle allows internal transfers to be externally monitored. the table below shows whether show cycle data is driven externally, and whether external bus arbitration can occur. to prevent bus conflict, external peripherals must not be enabled during show cycles. supv ?supervisor/unrestricted data space the supv bit places the sim global registers in either supervisor data space or user data space. the cpu16 in the MC68HC16Z1 operates only in supervisory mode. supv has no effect. mm ?module mapping 0 = internal modules are addressed from $7ff000 ?$7fffff. 1 = internal modules are addressed from $fff000 ?$ffffff. imb address lines addr[23:20] follow the logic state of addr19 unless externally driven. mm corre- sponds to imb addr23. if it is cleared, the sim maps imb modules into address space $7ff000 $7fffff, which is inaccessible to the cpu. modules remain inaccessible until reset occurs. mm can be written once. initialization software should set mm to logic level 1. iarb[3:0] ?interrupt arbitration field each module that can generate interrupt requests has an interrupt arbitration (iarb) field. arbitration between interrupt requests of the same priority is performed by serial contention between iarb field bit values. contention must take place whenever an interrupt request is acknowledged, even when there is only a single pending request. an iarb field must have a non-zero value for contention to take place. if an interrupt request from a module with an iarb field value of %0000 is recognized, the cpu16 pro- cesses a spurious interrupt exception. because the sim routes external interrupt requests to the cpu16, the sim iarb field value is used for arbitration between internal and external interrupts of the same priority. the reset value of iarb for the sim is %1111 (highest priority), and the reset iarb value for all other modules is %0000, which prevents sim interrupts from being discarded during initialization. shen action 00 show cycles disabled, external arbitration enabled 01 show cycles enabled, external arbitration disabled 10 show cycles enabled, external arbitration enabled 11 show cycles enabled, external arbitration enabled, internal activity is halted by a bus grant .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 47 3.3 system protection MC68HC16Z1 system protection includes a bus monitor, a halt monitor, a spurious interrupt monitor, and a software watchdog timer. these functions have been made integral to the microcontroller to re- duce the number of external components in a complete control system. the system protection control register controls system monitor functions, software watchdog clock prescaling, and bus monitor timing. in operating mode, this register can be written only once following power-on or reset, but can be read at any time. in test mode, it can be written at any time. swe ?software watchdog enable 0 = software watchdog disabled 1 = software watchdog enabled swp ?software watchdog prescale this bit controls the value of the software watchdog prescaler. 0 = software watchdog clock not prescaled 1 = software watchdog clock prescaled by 512 swt[1:0] ?software watchdog timing this field selects the divide ratio used to establish software watchdog time-out period. the following ta- ble gives the ratio for each combination of swp and swt bits. hme ?halt monitor enable 0 = disable halt monitor function 1 = enable halt monitor function bme ?bus monitor external enable 0 = disable bus monitor function for an internal to external bus cycle. 1 = enable bus monitor function for an internal to external bus cycle. bmt[1:0] ?bus monitor timing this field selects a bus monitor time-out period as shown in the following table. sypcr ?system protection control register $yffa21 7 6 5 4 3 2 1 0 swe swp swt hme bme bmt reset: 1 modclk 0 0 0 0 0 0 swp swt ratio 000 2 9 001 2 11 010 2 13 011 2 15 100 2 18 101 2 20 110 2 22 111 2 24 bmt bus monitor time-out period 00 64 system clocks (clk) 01 32 system clocks (clk) 10 16 system clocks (clk) 11 8 system clocks (clk) .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 48 MC68HC16Z1ts/d 3.3.1 bus monitor the internal bus monitor checks for excessively long response times during normal bus cycles (dsackx ) and during iack cycles (avec ). the monitor asserts berr if response time is excessive. dsackx and avec response times are measured in clock cycles. the maximum allowable response time can be selected by setting the bmt field. the monitor does not check dsackx response on the external bus unless the cpu16 initiates the bus cycle. the bme bit in the sypcr enables the internal bus monitor for internal to external bus cycles. if a system contains external bus masters, an external bus monitor must be implemented and the internal to external bus monitor option must be disabled. 3.3.2 halt monitor the halt monitor responds to an assertion of halt on the internal bus. a flag in the reset status register (rsr) indicates that the last reset was caused by the halt monitor. the halt monitor reset can be inhib- ited by the hme bit in the sypcr. 3.3.3 spurious interrupt monitor the spurious interrupt monitor issues berr if no interrupt arbitration occurs during iack cycle. 3.3.4 software watchdog register shown with read value the software watchdog is controlled by swe in sypcr. once enabled, the watchdog requires that a service sequence be written to swsr on a periodic basis. if servicing does not take place, the watchdog times out and issues a reset. this register can be written at any time, but returns zeros when read. perform a software watchdog service sequence as follows: ?write $55 to swsr. ?write $aa to swsr. both writes must occur before time-out in the order listed, but any number of instructions can be exe- cuted between the two writes. watchdog clock rate is affected by swp and swt in sypcr. when swt[1:0] are modified, a watchdog service sequence must be performed before the new time-out period takes effect. the reset value of swp is affected by the state of the modclk pin on the rising edge of reset, as shown in the following table. software watchdog time-out period is given in the following equation: time-out period = divide count/extal frequency swsr ?software service register $yffa27 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 reset: 0 0 0 0 0 0 0 0 modclk swp 01 10 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 49 3.4 system clock the system clock in the sim provides timing signals for the imb modules and for an external peripheral bus. because the MC68HC16Z1 is a fully static design, register and memory contents are not affected when clock rate changes. system hardware and software support changes in clock rate during opera- tion. the system clock signal can be generated in three ways. an internal phase-locked loop can synthesize the clock from an internal frequency source, an external frequency source, or the clock signal can be input from an external source. following is a block diagram of the clock submodule. figure 10 system clock block diagram 3.4.1 clock sources the state of the clock mode (modclk) pin during reset determines clock source. when modclk is held high during reset, the clock synthesizer generates a clock signal from either a crystal oscillator or an external reference input. clock synthesizer control register syncr determines operating frequency and various modes of operation. when modclk is held low during reset, the clock synthesizer is dis- abled, and an external system clock signal must be applied. when the synthesizer is disabled, syncr control bits have no effect. a reference crystal must be connected between the extal and xtal pins in order to use the internal oscillator. a 32.768-khz watch crystal is recommended ?these crystals are readily available and inex- pensive. MC68HC16Z1 clock synthesizer specifications are based upon a typical 32.768-khz crystal. sys clock block 32khz clkout extal phase comparator low-pass filter vco crystal oscillator system clock system clock control xtal xfc pin v ddsyn xfc 1 0.1 m f .01 m f 0.1 m f feedback divider 22 pf 2 10m 330 k w x y v ssi 22 pf 2 v ssi v ssi v ddsyn 1. must be low-leakage capacitor (insulation resistance 30,000 m w or greater). 2. capacitance based on a test circuit constructed with a daishinku dmx-38 32.768-khz crystal. .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 50 MC68HC16Z1ts/d if an external reference signal or an external system clock signal is applied through the extal pin, the xtal pin must be left floating. external reference signal frequency must be less than or equal to max- imum specified reference frequency. external system clock signal frequency must be less than or equal to maximum specified system clock frequency. when an external system clock signal is applied (pll not used), duty cycle of the input is critical, espe- cially at near maximum operating frequencies. the relationship between clock signal duty cycle and clock signal period is expressed: minimum external clock period = minimum external clock high/low time 50% ?percentage variation of external clock input duty cycle 3.4.2 clock synthesizer operation a voltage controlled oscillator (vco) generates the system clock signal. a portion of the clock signal is fed back to a divider/counter. the divider controls the frequency of one input to a phase comparator. the other phase comparator input is a reference signal, either from the internal oscillator or from an external source. the comparator generates a control signal proportional to the difference in phase be- tween its two inputs. the signal is low-pass filtered and used to correct vco output frequency. the synthesizer locks when vco frequency is identical to reference frequency. lock time is affected by the filter time constant and by the amount of difference between the two comparator inputs. whenever comparator input changes, the synthesizer must re-lock. lock status is shown by the slock bit in syn- cr. the MC68HC16Z1 does not come out of reset state until the synthesizer locks. crystal type, character- istic frequency, and layout of external oscillator circuitry affect lock time. the low-pass filter requires an external low-leakage capacitor, typically 0.1 m f, connected between the xfc and v ddsyn pins. v ddsyn is used to power the clock circuits. a separate power source increases mcu noise immunity and can be used to run the clock when the mcu is powered down. use a quiet power supply as the v ddsyn source, since pll stability depends on the vco, which uses this supply. place adequate ex- ternal bypass capacitors as close as possible to the v ddsyn pin to ensure stable operating frequency. when the clock synthesizer is used, control register syncr determines operating frequency and vari- ous modes of operation. because the cpu16 in the MC68HC16Z1 operates only in supervisor mode, syncr can be read or written at any time. the syncr x bit controls a divide by two prescaler that is not in the synthesizer feedback loop. setting x doubles clock speed without changing vco speed. there is no vco relock delay. the syncr w bit controls a 3-bit prescaler in the feedback divider. setting w increases vco speed by a factor of four. the syncr y field determines the count modulus for a modulo 64 down counter, causing it to divide by a value of y + 1. when either w or y value changes, there is a vco relock delay . clock frequency is determined by syncr bit settings as follows: f system = f reference [4(y + 1)(2 2w + x )] in order for the device to perform correctly, the clock frequency selected by the w, x, and y bits must be within the limits specified for the mcu. vco frequency is determined by: f vco = f system (2 ?x) the reset state of syncr ($3f00) produces a modulus-64 count ?system frequency is 256 times ref- erence frequency. .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 51 3.4.3 clock control the clock control circuits determine system clock frequency and clock operation under special circum- stances, such as loss of synthesizer reference or low-power mode. clock source is determined by the logic state of the modclk pin during reset. when the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper byte of syncr. bits in the lower byte show status of or control operation of internal and external clocks. because the cpu16 always operates in supervisor mode, syncr can be read or written at any time. w ?frequency control (vco) this bit controls a prescaler tap in the synthesizer feedback loop. setting the bit increases the vco speed by a factor of four. vco relock delay is required. x ?frequency control bit (prescale) this bit controls a divide by two prescaler that is not in the synthesizer feedback loop. setting the bit doubles clock speed without changing the vco speed. there is no vco relock delay. y[5:0] ?frequency control (counter) the y field controls the modulus down counter in the synthesizer feedback loop, causing it to divide by a value of y + 1. values range from 0 to 63. vco relock delay is required. ediv ?e clock divide rate 0 = eclk frequency is system clock divided by 8. 1 = eclk frequency is system clock divided by 16. eclk is an external m6800 bus clock available on pin addr23. refer to 3.5.13 chip selects for more information. slimp ?limp mode flag 0 = external crystal is vco reference. 1 = loss of crystal reference. when the on-chip synthesizer is used, loss of reference frequency causes slimp to be set. the vco continues to run using the base control voltage. maximum limp frequency is maximum specified system clock frequency. x-bit state affects limp frequency. slock ?synthesizer lock flag 0 = vco is enabled, but has not locked. 1 = vco has locked on the desired frequency (or system clock is external). the mcu maintains reset state until the synthesizer locks, but slock does not indicate synthesizer lock status until after the user writes to syncr. rsten ?reset enable 0 = loss of crystal causes the mcu to operate in limp mode. 1 = loss of crystal causes system reset. stsim ?stop mode system integration clock 0 = when lpstop is executed, the sim clock is driven from the crystal oscillator and the vco is turned off to conserve power. 1 = when lpstop is executed, the sim clock is driven from the vco. stext ?stop mode external clock 0 = when lpstop is executed, the clkout signal is held negated to conserve power. 1 = when lpstop is executed, the clkout signal is driven from the sim clock, as determined by the state of the stsim bit. syncr ?clock synthesizer control register $yffa04 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w x y ediv 0 0 slimp slock rsten stsim stext reset: 0 0 1 1 1 1 1 1 0 0 0 u u 0 0 0 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 52 MC68HC16Z1ts/d 3.4.4 periodic interrupt timer the periodic interrupt timer (pit) generates interrupts of specified priorities at specified intervals. timing for the pit is provided by a programmable prescaler driven by the system clock. this register contains information concerning periodic interrupt priority and vectoring. bits [10:0] can be read or written at any time. bits [15:11] are unimplemented and always return zero. pirql[2:0] ?periodic interrupt request level the following table shows what interrupt request level is asserted when a periodic interrupt is generat- ed. if a pit interrupt and an external irq of the same priority occur simultaneously, the pit interrupt is serviced first. the periodic timer continues to run when the interrupt is disabled. piv[7:0] ?periodic interrupt vector the bits of this field contain the vector generated in response to an interrupt from the periodic timer. when the sim responds, the periodic interrupt vector is placed on the bus. pitr contains the count value for the periodic timer. a zero value turns off the periodic timer. this reg- ister can be read or written at any time. ptp ?periodic timer prescaler control 1 = periodic timer clock prescaled by a value of 512 0 = periodic timer clock not prescaled the reset state of ptp is the complement of the state of the modclk signal during reset. pitm[7:0] ?periodic interrupt timing modulus field this is an 8-bit timing modulus. the period of the timer can be calculated as follows: pit period = [(pitm)(prescaler)(4)]/extal where pit period = periodic interrupt timer period pitm = periodic interrupt timer register modulus (pitr[7:0]) extal = crystal frequency prescaler = 512 or 1 depending on the state of the ptp bit in the pitr picr ?periodic interrupt control register $yffa22 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 pirql piv reset: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 pirql interrupt request level 000 periodic interrupt disabled 001 interrupt request level 1 010 interrupt request level 2 011 interrupt request level 3 100 interrupt request level 4 101 interrupt request level 5 110 interrupt request level 6 111 interrupt request level 7 pitr ?periodic interrupt timer register $yffa24 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ptp pitm reset: 0 0 0 0 0 0 0 modclk 0 0 0 0 0 0 0 0 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 53 3.5 external bus interface the external bus interface (ebi) transfers information between the internal mcu bus and external de- vices when the MC68HC16Z1 is operating in expanded modes. in fully expanded mode, the external bus has 24 address lines and 16 data lines. in partially expanded mode, the external bus has 24 ad- dress lines and 8 data lines. because the cpu16 in the MC68HC16Z1 drives only 20 of the 24 imb address lines, addr[23:20] follow the output state of addr19. the ebi provides dynamic sizing between 8-bit and 16-bit data accesses. it supports byte, word, and long-word transfers. ports are accessed through the use of asynchronous cycles controlled by the data transfer (siz1 and siz0) and data size acknowledge pins (dsack1 and dsack0 ). in fully expanded mode, both 8-bit and 16-bit data ports can be accessed; in partially expanded mode, only 8-bit ports can be accessed. multiple bus cycles may be required for a transfer to an 8-bit port. port width is the maximum number of bits accepted or provided during a bus transfer. external devices must follow the handshake protocol described below. control signals indicate the beginning of the cycle, the address space, the size of the transfer, and the type of cycle. the selected device controls the length of the cycle. strobe signals, one for the address bus and another for the data bus, indicate the validity of an address and provide timing information for data. the ebi operates in an asynchronous mode for any port width. to add flexibility and minimize the necessity for external logic, mcu chip select logic can be synchro- nized with ebi transfers. chip select logic can also provide internally-generated bus control signals for these accesses. refer to 3.5.13 chip selects for more information. 3.5.1 bus control signals the cpu initiates a bus cycle by driving the address, size, function code, and read/write outputs. at the beginning of the cycle, size signals siz0 and siz1 are driven along with the function code signals. the size signals indicate the number of bytes remaining to be transferred during an operand cycle. they are valid while the address strobe (as ) is asserted. the following table shows siz0 and siz1 encoding. the read/write (r/w ) signal determines the direction of the transfer during a bus cycle. this signal changes state, when required, at the beginning of a bus cycle, and is valid while as is asserted. r/w only tran- sitions when a write cycle is preceded by a read cycle or vice versa. the signal can remain low for two consecutive write cycles. 3.5.2 function codes function code signals fc[2:0] are automatically generated by the cpu16. the function codes can be considered address extensions that automatically select one of eight address spaces to which an ad- dress applies. these spaces are designated as either user or supervisor, and program or data spaces. because the cpu16 always operates in supervisor mode (fc2 always = 1), address spaces 0 to 3 are not used. address space 7 is designated cpu space. cpu space is used for control information not normally associated with read or write bus cycles. function codes are valid while as is asserted. table 11 size signal encoding siz1 siz0 transfer size 0 1 byte 1 0 word 1 1 3 byte 0 0 long word table 12 cpu16 address space encoding fc2 fc1 fc0 address space 1 0 0 reserved 1 0 1 data space 1 1 0 program space 1 1 1 cpu space .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 54 MC68HC16Z1ts/d 3.5.3 address bus address bus signals addr[19:0] define the address of the most significant byte to be transferred during a bus cycle. the mcu places the address on the bus at the beginning of a bus cycle. the address is valid while as is asserted. because the cpu16 in the MC68HC16Z1 does not drive addr[23:20], these lines follow the logic state of addr19. 3.5.4 address strobe as is a timing signal that indicates the validity of an address on the address bus and the validity of many control signals. it is asserted one-half clock after the beginning of a bus cycle. 3.5.5 data bus data bus signals data[15:0] comprise a bidirectional, non-multiplexed parallel bus that transfers data to or from the mcu. a read or write operation can transfer 8 or 16 bits of data in one bus cycle. during a read cycle, the data is latched by the mcu on the last falling edge of the clock for that bus cycle. for a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. the mcu places the data on the data bus one-half clock cycle after as is asserted in a write cycle. 3.5.6 data strobe data strobe (ds ) is a timing signal. for a read cycle, the mcu asserts ds to signal an external device to place data on the bus. ds is asserted at the same time as as during a read cycle. for a write cycle, ds signals an external device that data on the bus is valid. the mcu asserts ds one full clock cycle after the assertion of as during a write cycle. 3.5.7 bus cycle termination signals during bus cycles, external devices assert the data transfer and size acknowledge signals (dsack1 and dsack0 ). during a read cycle, the signals tell the mcu to terminate the bus cycle and to latch data. during a write cycle, the signals indicate that an external device has successfully stored data and that the cycle can end. these signals also indicate to the mcu the size of the port for the bus cycle just com- pleted. (refer to the discussion of dynamic bus sizing.) the bus error (berr ) signal is also a bus cycle termination indicator and can be used in the absence of dsack1 and dsack0 to indicate a bus error condition. it can also be asserted in conjunction with these signals, provided it meets the appropriate timing requirements. the internal bus monitor can be used to generate the berr signal for internal and internal-to-external transfers. when berr and halt are asserted simultaneously, the cpu16 takes a bus error exception. autovector signal (avec ) can terminate external irq pin interrupt acknowledge cycles. avec indicates that the mcu will internally generate a vector number to locate an interrupt handler routine. if it is con- tinuously asserted, autovectors will be generated for all external interrupt requests. avec is ignored during all other bus cycles. 3.5.8 data transfer mechanism the mcu architecture supports byte, word, and long-word operands, allowing access to 8- and 16-bit data ports through the use of asynchronous cycles controlled by the data transfer and size acknowledge inputs (dsack1and dsack0 ). 3.5.9 dynamic bus sizing the mcu dynamically interprets the port size of the addressed device during each bus cycle, allowing operand transfers to or from 8- and 16-bit ports. during an operand transfer cycle, the slave device sig- nals its port size and indicates completion of the bus cycle to the mcu through the use of the dsack0 and dsack1 inputs, as shown in the following table. .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 55 for example, if the mcu is executing an instruction that reads a long-word operand from a 16-bit port, the mcu latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits. the operation for an 8-bit port is similar, but requires four read cycles. the addressed device uses the dsack0 and dsack1 signals to indicate the port width. for instance, a 16-bit device always returns dsack0 = 1 and dsack1 = 0 for a 16-bit port, regardless of whether the bus cycle is a byte or word operation. dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. a 16-bit port must reside on data bus bits [15:0] and an 8-bit port must reside on data bus bits [15:8]. this minimizes the number of bus cycles needed to transfer data and ensures that the mcu transfers valid data. the mcu always attempts to transfer the maximum amount of data on all bus cycles. for a word oper- ation, it is assumed that the port is 16 bits wide when the bus cycle begins. operand bytes are desig- nated as shown in the following figure. op0 is the most significant byte of a long-word operand, and op3 is the least significant byte. the two bytes of a word-length operand are op0 (most significant) and op1. the single byte of a byte-length operand is op0. figure 11 operand byte order 3.5.10 operand alignment the data multiplexer establishes the necessary connections for different combinations of address and data sizes. the multiplexer takes the two bytes of the 16-bit bus and routes them to their required po- sitions. positioning of bytes is determined by the size and address outputs. siz1 and siz0 indicate the remaining number of bytes to be transferred during the current bus cycle. the number of bytes trans- ferred is equal to or less than the size indicated by siz1 and siz0, depending on port width. addr0 also affects the operation of the data multiplexer. during an operand transfer, addr[23:1] in- dicate the word base address of the portion of the operand to be accessed, and addr0 indicates the byte offset from the base. bear in mind the fact that addr[23:20] follow the state of addr19 in the MC68HC16Z1. 3.5.11 misaligned operands cpu16 processor architecture uses a basic operand size of 16 bits. an operand is misaligned when it overlaps a word boundary. this is determined by the value of addr0. when addr0 = 0 (an even ad- dress), the address is on a word and byte boundary. when addr0 = 1 (an odd address), the address is on a byte boundary only. a byte operand is aligned at any address; a word or long-word operand is misaligned at an odd address. table 13 effect of dsack signals dsack1 dsack0 result 1 1 insert wait states in current bus cycle 1 0 complete cycle ?data bus port size is 8 bits 0 1 complete cycle ?data bus port size is 16 bits 0 0 reserved operand byte order 31 24 23 16 15 8 7 0 long word op0 op1 op2 op3 three byte op0 op1 op2 word op0 op1 byte op0 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 56 MC68HC16Z1ts/d in the MC68HC16Z1, the largest amount of data that can be transferred by a single bus cycle is an aligned word. if the mcu transfers a long-word operand via a 16-bit port, the most significant operand word is transferred on the first bus cycle and the least significant operand word on a following bus cycle. the cpu16 can perform misaligned word transfers. this capability makes it software compatible with the mc68hc11 cpu. the cpu16 treats misaligned long-word transfers as two misaligned word trans- fers. 3.5.12 operand transfer cases the following table summarizes how operands are aligned for various types of transfers. opn entries are portions of a requested operand that are read or written during a bus cycle and are defined by siz1, siz0, and addr0 for that bus cycle. notes: 1. operands in parentheses are ignored by the cpu16 during read cycles. 2. three-byte transfer cases occur only as a result of a long word to byte transfer. 3. the cpu16 treats misaligned long-word transfers as two misaligned word transfers. 3.5.13 chip selects typical microcontrollers require additional hardware to provide external chip select signals. twelve in- dependently programmable chip selects provide fast two-cycle access to external memory or peripher- als. address block sizes of two kbytes to one mbyte can be selected. however, because addr[23:20] = addr19 in the cpu16, 512-kbyte blocks are the largest usable size. chip select assertion can be synchronized with bus control signals to provide output enable, read/write strobes, or interrupt acknowledge signals. logic can also generate dsack signals internally. a single dsack generator is shared by all circuits. multiple chip selects assigned to the same address and con- trol must have the same number of wait states. chip selects can also be synchronized with the eclk signal available on addr23. when a memory access occurs, chip select logic compares address space type, address, type of ac- cess, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in chip select registers. if all parameters match, the appropriate chip select signal is asserted. select sig- nals are active low. refer to the following block diagram of a single chip-select circuit. table 14 operand alignment transfer case siz1 siz0 addr0 dsack1 dsack0 data [15:8] data [7:0] byte to 8-bit port 0 1 x 1 0 op0 (op0) byte to 16-bit port (even) 0 1 0 0 x op0 (op0) byte to 16-bit port (odd) 0 1 1 0 x (op0) op0 word to 8-bit port (aligned) 1 0 0 1 0 op0 (op1) word to 8-bit port (misaligned) 1 0 1 1 0 op0 (op0) word to 16-bit port (aligned) 1 0 0 0 x op0 op1 word to 16-bit port (misaligned) 1 0 1 0 x (op0) op0 3 byte to 8-bit port (aligned) 2 1 1 0 1 0 op0 (op1) 3 byte to 8-bit port (misaligned) 2 1 1 1 1 0 op0 (op0) 3 byte to 16-bit port (aligned) 3 1 1 0 0 x op0 op1 3 byte to 16-bit port (misaligned) 2 1 1 1 0 x (op0) op0 long word to 8-bit port (aligned) 0 0 0 1 0 op0 (op1) long word to 8-bit port (misaligned) 3 1 0 1 1 0 op0 (op0) long word to 16-bit port (aligned) 0 0 0 0 x op0 op1 long word to 16-bit port (misaligned) 3 1 0 1 0 x (op0) op0 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 57 figure 12 chip-select circuit block diagram because initialization software usually resides in a peripheral memory device controlled by the chip-se- lect circuits, a csboot register provides default reset values to support bootstrap operation. if a chip select function is given the same address as a microcontroller module or memory array, an access to that address goes to the module or array and the chip select signal is not asserted. each chip select pin can have two or more functions. chip select configuration out of reset is determined by operating mode. in all modes, the boot rom select signal is automatically asserted out of reset. in single-chip mode, all chip select pins except cs10 and cs0 are configured for alternate functions or discrete output. in expanded modes, appropriate pins are configured for chip select operation, but chip select signals cannot be asserted until a transfer size is chosen. in fully expanded mode, data bus pins can be held low to enable alternate functions for chip select pins. the following table lists allocation of chip-selects and discrete outputs on the pins of the mcu. pin chip select discrete outputs csboot csboot ? br cs0 ? bg cs1 ? bgack cs2 ? fc0 cs3 pc0 fc1 cs4 pc1 fc2 cs5 pc2 addr19 cs6 pc3 addr20 cs7 pc4 addr21 cs8 pc5 addr22 cs9 pc6 addr23 cs10 eclk chip sel block avec generator dsack generator pin assignment register pin data register base address register timing and control address comparator option compare option register avec dsack pin bus control internal signals address 1 of 12 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 58 MC68HC16Z1ts/d 3.5.13.1 chip-select registers pin assignment registers (cspar) determine functions of chip select pins. pin assignment registers also determine port size (8- or 16-bit) for dynamic bus allocation. a pin data register (portc) latches discrete output data. blocks of addresses are assigned to each chip select function. block sizes of 2 kbytes to 1 mbyte can be selected by writing values to the appropriate base address register (csbar). however, because the logic state of addr20 is always the same as the state of addr19 in the MC68HC16Z1, the largest usable block size is 512 kbytes. address blocks for separate chip select functions can overlap. chip select option registers (csor) determine timing of and conditions for assertion of chip select sig- nals. eight parameters, including operating mode, access size, synchronization, and wait state insertion can be specified. initialization code often resides in a peripheral memory device controlled by the chip select circuits. a set of special chip select functions and registers (csorbt, csbarbt) is provided to support bootstrap operation. 3.5.13.2 pin assignment registers the pin assignment registers contain pairs of bits that determine the function of pins in other chip-select registers. alternate functions of the associated pins are shown in parentheses. bits [15:14] ?not used these bits always read zero; write has no effect. bits [15:10] ?not used these bits always read zero; write has no effect. the following table shows pin assignment register encoding. a pin programmed as a discrete output drives an external signal to the value specified in the port c data register (portc), with the following exceptions: 1. no discrete output function is available on pins br , bg , or bgack . 2. addr23 provides the eclk output rather than a discrete output signal. cspar0 ?chip-select pin assignment register 0 $yffa44 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 cs5 (fc2) cs4 (fc1) cs3 (fc0) cs2 (bgack) cs1 (bg) cs0 (br) csboot reset: 0 0 db2 1 db2 1 db2 1 db1 1 db1 1 db1 1 1 db0 cspar1 ?chip-select pin assignment register 1 $yffa46 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 cs10 (addr23) cs9 (addr22) cs8 (addr21) cs7 (addr20) cs6 (addr19) reset: 0 0 0 0 0 0 db7 1 db6 1 db5 1 db4 1 db3 1 bit pair description 00 discrete output 01 default function 10 chip select (8-bit port) 11 chip select (16-bit port) .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 59 when a pin is programmed for discrete output or default function, internal chip-select logic still functions and can be used to generate dsack or avec internally on an address match. port size is determined when a pin is assigned as a chip select. when a pin is assigned to an 8-bit port, the chip select is asserted at all addresses within the block range. if a pin is assigned to a 16-bit port, the upper/lower byte field of the option register selects the byte with which the chip select is associated. the notation db# in a cspar reset block indicates that a bit goes to the logic level of that data bus pin on reset. either default function (01) or chip-select function (11) can be encoded. because of internal pull-up, db pins are driven to logic level one by a weak pull-up during reset. encoding is for chip-select function unless a data line is held low during reset. note that bus loading can overcome the weak pull- up, and hold pins low during reset. because addr[23:20] follow the state of addr19 in the cpu16, db[7:4] have limited use. 3.5.13.3 base address registers a base address is the starting address for the block enabled by a given chip select. block size deter- mines the extent of the block above the base address. each chip select has an associated base register so that an efficient address map can be constructed for each application. *addr[23:20] follow the state of addr19 in the MC68HC16Z1. addr[23:20] must match addr19 for the chip select to be active. blksz ?block size field this field determines the size of the block that must be enabled by the chip select. the following table shows bit encoding for the base address registers block size field. addr[23:20] is at the same logic level as addr19 during normal operation. csbarbt ?chip-select base address register boot rom $yffa48 1514131211109876543210 addr 23* addr 22* addr 21* addr 20* addr 19 addr 18 addr 17 addr 16 addr 15 addr 14 addr 13 addr 12 addr 11 blksz reset: 0 000000000000111 csbar[10:0] ?chip-select base address registers $yffa4c?yffa74 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 addr 23* addr 22* addr 21* addr 20* addr 19 addr 18 addr 17 addr 16 addr 15 addr 14 addr 13 addr 12 addr 11 blksz reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 block size field block size address lines compared 000 2 k addr[23:11] 001 8 k addr[23:13] 010 16 k addr[23:14] 011 64 k addr[23:16] 100 128 k addr[23:17] 101 256 k addr[23:18] 110 512 k addr[23:19] 111 512 k addr[23:20] .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 60 MC68HC16Z1ts/d addr[15:3] ?base address field this field sets the starting address of a particular address space. the address compare logic uses only the most significant bits to match an address within a block. the value of the base address must be a multiple of block size. base address register diagrams show how base register bits correspond to ad- dress lines. because addr20 = addr19 in the cpu16, maximum block size is 512 kbytes. because addr[23:20] follow the logic state of addr19, addresses from $080000 to $f7ffff are inaccessible. blocks can be based above this dead zone, but the effect of addr19 must be considered. 3.5.13.4 option registers the option registers contain eight fields that determine timing of and conditions for assertion of chip- select signals and make the chip selects useful for generating peripheral control signals. all bits in the base address register and the option register must be satisfied to assert a chip-select signal. the bits must also be satisfied to provide dsack or autovector support. the option register for csboot , which is csorbt, contains special reset values that support boot- strap operations from peripheral memory devices. the following bit descriptions apply to both csorbt and csor[10:0] option registers. mode ?asynchronous/synchronous mode 0 = asynchronous mode selected (chip select assertion determined by internal or external bus con- trol signals) 1 = synchronous mode selected (chip select assertion synchronized with eclk signal) in asynchronous mode, the chip select is asserted synchronized with as or ds . byte ?upper/lower byte option this field is used only when the chip-select 16-bit port option is selected in the pin assignment register. the following table lists upper/lower byte options. if an interrupting device does not provide a vector number, an autovector acknowledge must be gener- ated. the bus cycle is terminated by asserting avec . this can be done either by asserting the avec pin or by generating avec internally, using the chip select option register. csorbt ?chip-select option register boot rom $yffa4a 1514131211109876543210 mode byte r/ w strb dsack space ipl avec reset: 0 111101101110000 csor[10:0] ?chip-select option registers $yffa4e?yffa76 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mode byte r/ w strb dsack space ipl avec reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 byte description 00 disable 01 lower byte 10 upper byte 11 both bytes .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 61 r/w ?read/write this field causes a chip select to be asserted only for a read, only for a write, or for both read and write. refer to the following table for options available. strb ?address strobe/data strobe 1 = data strobe 0 = address strobe this bit controls the timing for assertion of a chip select in asynchronous mode. selecting address strobe causes chip select to be asserted synchronized with address strobe. selecting data strobe caus- es chip select to be asserted synchronized with data strobe. dsack ?data strobe acknowledge this field specifies the source of dsack in asynchronous mode. it also allows the user to adjust bus timing with internal dsack generation by controlling the number of wait states that are inserted to op- timize bus speed in a particular application. the following table shows the dsack field encoding. the fast termination encoding (1110) is used for two-cycle access to external memory. the dsack field is not used in synchronous mode because a bus cycle is only performed as a syn- chronous operation. when a match condition occurs on a chip select programmed for synchronous op- eration, the chip select signals the ebi that an e-clock cycle is pending. space ?address space use this option field to select an address space for the chip-select logic. the cpu16 normally operates in supervisor space, but interrupt acknowledge must take place in cpu space. r/ w description 00 reserved 01 read only 10 write only 11 read/write dsack description 0000 no wait states 0001 1 wait state 0010 2 wait states 0011 3 wait states 0100 4 wait states 0101 5 wait states 0110 6 wait states 0111 7 wait states 1000 8 wait states 1001 9 wait states 1010 10 wait states 1011 11 wait states 1100 12 wait states 1101 13 wait states 1110 fast termination 1111 external dsack space field address space 00 cpu space 01 user space 10 supervisor space 11 supervisor/user space .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 62 MC68HC16Z1ts/d ipl ?interrupt priority level if the space field is set for cpu space (00), chip-select logic can be used for interrupt acknowledge. during an iack cycle, the priority level on address lines addr[3:1] is compared to the value in the ipl field. if the values are the same, a chip select can be asserted, provided that other option register con- ditions are met. the following table shows ipl field encoding. this field only affects the response of chip selects and does not affect interrupt recognition by the cpu. any level means that chip select is asserted regardless of the level of the iack cycle. avec ?autovector enable 1 = autovector enabled 0 = external interrupt vector enabled this field selects one of two methods of acquiring an interrupt vector during the iack cycle. it is not usually used in conjunction with a chip-select pin. if the chip select is configured to trigger on an iack cycle (space = 00) and the avec field is set to one, the chip select automatically generates an avec in response to the iack cycle. otherwise, the vector must be supplied by the requesting device. the avec bit must not be used in synchronous mode, as autovector response timing can vary because of eclk synchronization. the data register controls the state of pins programmed as discrete outputs. when a pin is assigned as a discrete output, the value in this register appears at the output. pc[6:0] correspond to cs[9:3]. this is a read/write register. bit 7 is not used. writing to this bit has no effect; it always reads zero. 3.5.14 general-purpose input/output sim pins can be configured as two general-purpose i/o ports, e and f. the following paragraphs de- scribe registers that control the ports. a write to the port e data register is stored in the internal data latch and, if any port e pin is con?ured as an output, the value stored for that bit is driven on the pin. a read of the port e data register (porte) returns the value at the pin only if the pin is con?ured as a discrete input. otherwise, the value read is ipl description 000 any level 001 ipl1 010 ipl2 011 ipl3 100 ipl4 101 ipl5 110 ipl6 111 ipl7 portc ?port c data register $yffa41 7 6 5 4 3 2 1 0 0 pc6 pc5 pc4 pc3 pc2 pc1 pc0 reset: 0 1 1 1 1 1 1 1 porte ?port e data register $yffa11, $yffa13 7 6 5 4 3 2 1 0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 reset: u u u u u u u u .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 63 the value stored in the register. port e is a single register that can be accessed in two locations. it can be read or written at any time. the bits in this register control the direction of the pin drivers when the pins are con?ured as i/o. any bit in this register set to one con?ures the corresponding pin as an output. any bit in this register cleared to zero con?ures the corresponding pin as an input. this register can be read or written at any time. the bits in this register control the function of each port e pin. any bit set to one defines the correspond- ing pin as a bus control signal, with the function shown in the register diagram. any bit cleared to zero defines the corresponding pin as an i/o pin, controlled by porte and ddre. data bus bit 8 controls the state of this register following reset. if db8 is set to one during reset, the register is set to $ff, which de?es all port e pins as bus control signals. if db8 is cleared to zero during reset, this register is set to $00, de?ing all port e pins as i/o pins. note pe3 is not connected to a pin. pepa3 returns 1 when read; dde3 and pe3 bits can be read and written, but have no function. the write to the port f data register is stored in the internal data latch, and if any port f pin is con?ured as an output, the value stored for that bit is driven on the pin. a read of the port f data register (portf) returns the value at the pin only if the pin is con?ured as a discrete input. otherwise, the value read is the value stored in the register. port f is a single register that can be accessed in two locations. it can be read or written at any time. the bits in this register control the direction of the pin drivers when the pins are con?ured as i/o. any bit in this register set to one con?ures the corresponding pin as an output. any bit in this register cleared to zero con?ures the corresponding pin as an input. ddre ?port e data direction register $yffa15 7 6 5 4 3 2 1 0 dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 reset: 0 0 0 0 0 0 0 0 pepar ?port e pin assignment register $yffa17 7 6 5 4 3 2 1 0 pepa7 (siz1) pepa6 (siz0) pepa5 ( as ) pepa4 ( ds ) pepa3 pepa2 ( avec ) pepa1 dsack1 pepa0 dsack0 reset: db8 db8 db8 db8 db8 db8 db8 db8 portf ?port f data register $yffa19, $yffa1b 7 6 5 4 3 2 1 0 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 reset: u u u u u u u u ddrf ?port f data direction register $yffa1d 7 6 5 4 3 2 1 0 ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 reset: 0 0 0 0 0 0 0 0 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 64 MC68HC16Z1ts/d the bits in this register control the function of each port f pin. any bit set to one defines the correspond- ing pin to be an interrupt request input as defined in the register diagram. any bit cleared to zero defines the corresponding pin as an i/o pin, controlled by the port f data and data direction registers. the mod- clk signal has no function after reset. data bus bit 9 controls the state of this register following reset. if db9 is set to one during reset, the register is set to $ff, which de?es all port f pins as interrupt request inputs. if db9 is cleared to zero during reset, this register is set to $00, de?ing all port f pins as i/o pins. 3.6 resets reset procedures handle system initialization and recovery from catastrophic failure. the MC68HC16Z1 performs resets with a combination of hardware and software. the system integration module determines whether a reset is valid, asserts control signals, performs basic system configura- tion and boot rom selection based on hardware mode-select inputs, then passes control to the cpu16. reset occurs when an active low logic level on the reset pin is clocked into the sim. resets are gated by the clkout signal. asynchronous resets are assumed to be catastrophic. an asynchronous reset can occur on any clock edge. synchronous resets are timed to occur at the end of bus cycles. if there is no clock when reset is asserted, reset does not occur until the clock starts. resets are clocked in order to allow completion of write cycles in progress at the time reset is asserted. reset is the highest-priority cpu16 exception. any processing in progress is aborted by the reset ex- ception, and cannot be restarted. only essential tasks are performed during reset exception processing. other initialization tasks must be accomplished by the exception handler routine. the reset status register contains a bit for each reset source in the mcu. a bit set to one indicates what type of reset has occurred. when multiple reset sources occur at the same time, more than one bit in rsr can be set. the reset status register is updated by the reset control logic when the mcu comes out of reset. this register can be read at any time. a write has no effect. ext ?external reset reset was caused by an external signal. pow ?power-up reset reset was caused by the power-up reset circuit. sw ?software watchdog reset reset was caused by the software watchdog circuit. hlt ?halt monitor reset reset was caused by the system protection submodule halt monitor. loc ?loss of clock reset reset was caused by loss of clock submodule frequency reference. this reset can only occur if the rsten bit in the clock submodule is set and the vco is enabled. pfpar ?port f pin assignment register $yffa1f 7 6 5 4 3 2 1 0 pfpa7 ( irq7 ) pfpa6 ( irq6 ) pfpa5 ( irq5 ) pfpa4 ( irq4 ) pfpa3 ( irq3 ) pfpa2 ( irq2 ) pfpa1 ( irq1 ) pfpa0 (modclk) reset: db9 db9 db9 db9 db9 db9 db9 db9 rsr ?reset status register $yffa07 7 6 5 4 3 2 1 0 ext pow sw hlt 0 loc sys tst .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 65 sys ?system reset reset was caused by a cpu reset instruction. because the cpu16 has no reset instruction, this bit is not used on the MC68HC16Z1 and always reads zero. tst ?test submodule reset reset was caused by the test submodule. 3.6.1 reset mode selection the logic states of certain data bus pins during reset determine sim operating con?uration. in addition, the state of the modclk pin determines system clock source and the state of the pin determines what happens during subsequent breakpoint assertions. the following table is a summary of reset mode se- lection options. table 15 reset mode selection mode select pin default function (pin left high) alternate function (pin pulled low) data0 csboot 16-bit csboot 8-bit data1 cs0 br cs1 bg cs2 bgack data2 cs3 fc0 cs4 fc1 cs5 fc2 data3 cs6 addr19 data4 cs7 ?s6 addr[20:19] data5 cs8 ?s6 addr[21:19] data6 cs9 ?s6 addr[22:19] data7 cs10 ?s6 addr[23:19] data8 dsack0 , dsack1 , porte avec , ds , as , size data9 irq7 ?rq1 portf modclk data11 test mode disabled test mode enabled data14 rom stop = 0 (enabled) rom stop = 1 (disabled) modclk vco = system clock extal = system clock bkpt background mode disabled background mode enabled .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 66 MC68HC16Z1ts/d 3.6.2 mcu module pin function during reset generally, module pins default to port functions, and input/output ports are set to input state. this is ac- complished by disabling pin functions in the appropriate control registers, and by clearing the appropri- ate port data direction registers. refer to individual module sections in this manual for more information. the following table is summary of module pin function out of reset. 3.6.3 reset timing the reset input must be asserted for a specified minimum period in order for reset to occur. external reset assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus monitor time-out period) in order to protect write cycles from being aborted by reset. while reset is asserted, sim pins are either in an inactive, high impedance state or are driven to their inactive states. when an external device asserts reset for the proper period, reset control logic clocks the signal into an internal latch. the control logic drives the reset pin low for an additional 512 clkout cycles after it detects that the reset signal is no longer being externally driven, to guarantee this length of reset to the entire system. if an internal source asserts a reset signal, the reset control logic asserts reset for a minimum of 512 cycles. if the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert reset until the internal reset signal is negated. after 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for 10 cy- cles. at the end of this 10-cycle period, the reset input is tested. when the input is at logic level one, reset exception processing begins. if, however, the reset input is at logic level zero, the reset control logic drives the pin low for another 512 cycles. at the end of this period, the pin again goes to high- impedance state for 10 cycles, then it is tested again. the process repeats until reset is released. table 16 module pin functions module pin mnemonic function adc pada[7:0]/an[7:0] discrete input v rh reference voltage v rl reference voltage cpu dsi/ipipe1 dsi/ipipe1 dso/ipipe0 dso/ipipe0 bkpt /dsclk bkpt /dsclk gpt pgp7/ic4/oc5 discrete input pgp[6:3]/oc[4:1] discrete input pgp[2:0]/ic[3:1] discrete input pai discrete input pclk discrete input pwma, pwmb discrete output qsm pqs7/txd discrete input pqs[6:4]/pcs[3:1] discrete input pqs3/pcs0/ss discrete input pqs2/sck discrete input pqs1/mosi discrete input pqs0/miso discrete input rxd rxd .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 67 3.6.4 power-on reset when the sim clock synthesizer is used to generate system clocks, power-on reset involves special cir- cumstances related to application of system and clock synthesizer power. regardless of clock source, voltage must be applied to clock synthesizer power input pin v ddsyn , in order for the mcu to operate. the following discussion assumes that v ddsyn is applied before and during reset ?this minimizes crys- tal start-up time. when v ddsyn is applied at power-on, start-up time is affected by specific crystal param- eters and by oscillator circuit design. v dd ramp-up time also affects pin state during reset. during power-on reset, an internal circuit in the sim drives the imb internal and external reset lines. the circuit releases the internal reset line as v dd ramps up to the minimum specified value, and sim pins are initialized. when v dd reaches minimum value, the clock synthesizer vco begins operation, and clock frequency ramps up to limp mode frequency. the external reset signal remains asserted until the clock synthesizer pll locks and 512 clkout cycles elapse. the sim clock synthesizer provides clock signals to the other mcu modules. after the clock is running and the internal reset signal is asserted for four clock cycles, these modules reset. v dd ramp time and vco frequency ramp time determine how long the four cycles take. worst case is approximately 15 mil- liseconds. during this period, module port pins may be in an indeterminate state. while input-only pins can be put in a known state by means of external pull-up resistors, external logic on input/output or out- put-only pins must condition the lines during this time. active drivers require high-impedance buffers or isolation resistors to prevent conflict. 3.6.4.1 use of three state control pin asserting the three-state control (tsc) input causes the mcu to put all output drivers in an inactive, high-impedance state. the signal must remain asserted for 10 clock cycles in order for drivers to change state. there are certain constraints on use of tsc during power-up reset: when the internal clock synthesizer is used (modclk held high during reset), synthesizer ramp- up time affects how long the 10 cycles take. worst case is approximately 20 milliseconds from tsc assertion. when an external clock signal is applied (modclk held low during reset), pins go to high-imped- ance state as soon after tsc assertion as 10 clock pulses have been applied to the extal pin. when tsc assertion takes effect, internal signals are forced to values that can cause inadvertent mode selection. once the output drivers change state, the mcu must be powered down and restarted before normal operation can resume. 3.7 interrupts interrupt recognition and servicing involve complex interaction between the central processing unit, the system integration module, and a device or module requesting interrupt service. the cpu16 provides for eight levels of interrupt priority (0?), seven automatic interrupt vectors, and 200 assignable interrupt vectors. all interrupts with priorities less than seven can be masked by the in- terrupt priority (ip) field in the condition code register. the cpu16 handles interrupts as a type of asyn- chronous exception. interrupt recognition is based on the states of interrupt request signals irq[7:1] and the ip mask value. each of the signals corresponds to an interrupt priority. irq1 has the lowest priority, and irq7 has the highest priority. the ip field consists of three bits (ccr[7:5]). binary values %000 to %111 provide eight priority masks. masks prevent an interrupt request of a priority less than or equal to the mask value (except for irq7 ) from being recognized and processed. when ip contains %000, no interrupt is masked. during excep- tion processing, the ip field is set to the priority of the interrupt being serviced. interrupt request signals can be asserted by external devices or by microcontroller modules. request lines are connected internally by means of a wired nor ?simultaneous requests of differing priority .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 68 MC68HC16Z1ts/d can be made. internal assertion of an interrupt request signal does not affect the logic state of the cor- responding mcu pin. external interrupt requests are routed to the cpu16 via the external bus interface and sim interrupt con- trol logic ?the cpu treats external interrupt requests as though they come from the sim. external irq [6:1] are active-low level-sensitive inputs. external is an active-low transition-sensitive in- put ?it requires both an edge and a voltage level for validity. irq [6:1] are maskable.irq7 is nonmaskable. the irq7 input is transition-sensitive in order to prevent redundant servicing and stack overflow. a nonmaskable interrupt is generated each time irq7 is as- serted, and each time the priority mask changes from %111 to a lower number while irq7 is asserted. interrupt requests are sampled on consecutive falling edges of the system clock. interrupt request input circuitry has hysteresis ?to be valid, a request signal must be asserted for at least two consecutive clock periods. valid requests do not cause immediate exception processing, but are left pending. pend- ing requests are processed at instruction boundaries or when exception processing of higher-priority exceptions is complete. the cpu16 does not latch the priority of a pending interrupt request. if an interrupt source of higher priority makes a service request while a lower priority request is pending, the higher priority request is serviced. if an interrupt request of equal or lower priority than the current ip mask value is made, the cpu does not recognize the occurrence of the request in any way. 3.7.1 interrupt acknowledge and arbitration interrupt acknowledge bus cycles are generated during exception processing. when the cpu16 de- tects one or more interrupt requests of a priority higher than the interrupt priority mask value, it performs a cpu space read from address $fffff : [ip] : 1. the cpu space read cycle performs two functions: it places a mask value corresponding to the highest priority interrupt request on the address bus, and it acquires an exception vector number from the inter- rupt source. the mask value also serves two purposes: it is latched into the ccr ip field in order to mask lower-priority interrupts during exception processing, and it is decoded by modules that have re- quested interrupt service to determine whether the current interrupt acknowledge cycle pertains to them. modules that have requested interrupt service decode the ip value placed on the address bus at the beginning of the interrupt acknowledge cycle, and if their requests are at the specified ip level, respond to the cycle. arbitration between simultaneous requests of the same priority is performed by means of serial contention between module interrupt arbitration (iarb) field bit values. each module that can make an interrupt service request, including the sim, has an iarb field in its con- figuration register. an iarb field can be assigned a value from %0001 (lowest priority) to %1111 (high- est priority). a value of %0000 in an iarb field causes the cpu16 to process a spurious interrupt exception when an interrupt from that module is recognized. because the ebi manages external interrupt requests, the sim iarb value is used for arbitration be- tween internal and external interrupt requests. the reset value of iarb for the sim is %1111, and the reset iarb value for all other modules is %0000. initialization software must assign different iarb val- ues in order to implement an arbitration scheme. each module must have a unique iarb value. when two or more iarb fields have the same nonzero value, the cpu16 interprets multiple vector numbers simultaneously, with unpredictable consequences. arbitration must always take place, even when a single source requests service. this point is important for two reasons: the cpu interrupt acknowledge cycle is not driven on the external bus unless the sim wins contention, and failure to contend causes an interrupt acknowledge bus cycle to be terminated by a bus error, which causes a spurious interrupt exception to be taken. when arbitration is complete, the dominant module must place an interrupt vector number on the data bus and terminate the bus cycle. in the case of an external interrupt request, because the interrupt ac- .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 69 knowledge cycle is transferred to the external bus, an external device must decode the mask value and respond with a vector number, then generate bus cycle termination signals. if the device does not re- spond in time, a spurious interrupt exception is taken. the periodic interrupt timer (pit) in the sim can generate internal interrupt requests of specific priority at predetermined intervals. by hardware convention, pit interrupts are serviced before external inter- rupt service requests of the same priority. refer to 3.4.4 periodic interrupt timer for more information. 3.7.2 interrupt processing summary a summary of the interrupt processing sequence follows. when the sequence begins, a valid interrupt service request has been detected and is pending. ?the cpu finishes higher priority exception processing or reaches an instruction boundary. ?processor state is stacked, then the ccr pk extension field is cleared. ?the interrupt acknowledge cycle begins: ?fc[2:0] are driven to %111 (cpu space) encoding. ?the address bus is driven as follows. addr[23:20] = %1111; addr[19:16] = %1111, which indicates that the cycle is an interrupt acknowledge cpu space cycle; addr[15:4] = %11111111111; addr[3:1] = the priority of the interrupt request being acknowledged; and addr0 = %1. ?request priority is latched into the ccr ip field from the address bus. ?modules or external peripherals that have requested interrupt service decode the priority value in addr[3:1]. if request priority is the same as the priority value in the address, iarb contention takes place. when there is no contention, the spurious interrupt monitor asserts, and a spurious interrupt exception is processed. ?after arbitration, the interrupt acknowledge cycle can be completed in one of three ways: ?the dominant interrupt source supplies a vector number and signals appropriate to the access. the cpu16 acquires the vector number. ?the signal is asserted (the signal can be asserted by the dominant interrupt source or the pin can be tied low), and the cpu16 generates an autovector number corresponding to interrupt priority. ?the bus monitor asserts and the cpu16 generates the spurious interrupt vector number. ?the vector number is converted to a vector address. ?the content of the vector address is loaded into the pc, and the processor transfers control to the exception handler routine. 3.8 factory test block the test submodule supports scan-based testing of the various mcu modules. it is integrated into the sim to support production test. 3.8.1 test registers test submodule registers are intended for motorola use. register names and addresses are provided to indicate that these addresses are occupied. simtr ? system integration test register $yffa02 simtre ? system integration test register (e clock) $yffa08 tstmsra ? master shift register a $yffa30 tstmsrb ? master shift register b $yffa32 tstsc ? test module shift count $yffa34 tstrc ? test module repetition count $yffa36 creg ? test submodule control register $yffa38 dreg ? distributed register $yffa3a .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 70 MC68HC16Z1ts/d .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 71 4 analog-to-digital converter module the adc is a unipolar, successive-approximation converter with eight modes of operation. it has se- lectable 8- or 10-bit resolution. accuracy is 1 count (1 lsb) in 8-bit mode and 2.5 counts (2.5 lsb) in 10-bit mode. monotonicity is guaranteed in both modes. with a 16.78-mhz clock, the adc can per- form an 8-bit single conversion (4-clock sample) in 8 microseconds, a 10-bit single conversion in 9 mi- croseconds. adc functions can be grouped into three subsystems: an analog front end, a digital control section, and a bus interface. a block diagram of the converter appears on the following page. 4.1 analog subsystem the analog front end consists of a multiplexer, input sample buffer amplifier, a resistor-capacitor array, and a high-gain comparator. the multiplexer selects one of eight internal or eight external signal sourc- es for conversion. the resistor capacitor (rc) array performs two functions. it acts as a sample/hold circuit, and it provides the digital-to-analog comparison output necessary for successive approximation conversion. the comparator indicates whether each successive output of the rc array is higher or low- er than the sampled input. 4.2 digital control subsystem the digital control section includes conversion sequence control logic, channel and reference select logic, successive approximation register, eight result registers, a port data register, and control/status registers. it controls the multiplexer and the output of the rc array during the sample and conversion periods, stores the results of comparison in the successive-approximation register, then transfers the result to a result register. 4.3 bus interface subsystem the bus interface contains logic necessary to interface the adc to the intermodule bus. the adc is designed to act as a slave device on the bus. the interface must respond with appropriate bus cycle termination signals and must supply appropriate interface timing to the other submodule. .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 72 MC68HC16Z1ts/d figure 13 analog-to-digital converter block diagram sar rc dac array and comparator analog mux and sample buffer clk select/ prescale pada6/an6 pada5/an5 pada4/an4 pada3/an3 pada2/an2 pada1/an1 pada0/an0 v rh v rl adc bus interface unit mode and timing control z1 adc block result 7 result 6 result 5 result 4 result 3 result 2 result 1 result 0 pada7/an7 amplifier v dda v ssa supply intermodule bus (imb) reference port ada data register internal connections reserved reserved reserved v rh v rl (v rh ?v rl )/2 reserved reserved .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 73 y = m111, where m is the logic state of the modmap (mm) bit in the simcr 4.4 adc registers use the module configuration register to initialize the adc. table 17 adc address map address 15 8 7 0 $yff700 module configuration (adcmcr) $yff702 factory test (adtest) $yff704 (reserved) $yff706 port ada data (portada) $yff708 (reserved) $yff70a adc control 0 (adctl0) $yff70c adc control 1 (adctl1) $yff70e adc status (adstat) $yff710 right-justified unsigned result 0 (rjurr0) $yff712 right-justified unsigned result 1 (rjurr1) $yff714 right-justified unsigned result 2 (rjurr2) $yff716 right-justified unsigned result 3 (rjurr3) $yff718 right-justified unsigned result 4 (rjurr4) $yff71a right-justified unsigned result 5 (rjurr5) $yff71c right-justified unsigned result 6 (rjurr6) $yff71e right-justified unsigned result 7 (rjurr7) $yff720 left-justified signed result 0 (ljsrr0) $yff722 left-justified signed result 1 (ljsrr1) $yff724 left-justified signed result 2 (ljsrr2) $yff726 left-justified signed result 3 (ljsrr3) $yff728 left-justified signed result 4 (ljsrr4) $yff72a left-justified signed result 5 (ljsrr5) $yff72c left-justified signed result 6 (ljsrr6) $yff72e left-justified signed result 7 (ljsrr7) $yff730 left-justified unsigned result 0 (ljurr0) $yff732 left-justified unsigned result 1 (ljurr1) $yff734 left-justified unsigned result 2 (ljurr2) $yff736 left-justified unsigned result 3 (ljurr3) $yff738 left-justified unsigned result 4 (ljurr4) $yff73a left-justified unsigned result 5 (ljurr5) $yff73c left-justified unsigned result 6 (ljurr6) $yff73e left-justified unsigned result 7 (ljurr7) adcmcr ?adc module configuration register $yff700 15 14 13 12 8 7 6 0 stop frz not used supv not used reset: 1 0 0 0 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 74 MC68HC16Z1ts/d stop ?stop mode 0 = normal operation 1 = low-power operation stop places the adc in low-power state by disabling the adc clock and powering down the analog circuitry. setting stop aborts any conversion in progress. stop is set to logic level one at reset and can be cleared to logic level zero by the cpu. clearing stop enables normal adc operation. however, because analog circuitry bias current has been turned off, there is a period of recovery before output stabilization. frz[1:0] ?freeze 1 use the frz field to determine adc response to assertion of the ifreeze signal. the following table shows possible responses. supv ?supervisor/unrestricted 0 = unrestricted access 1 = supervisor access supv defines access to assignable adc registers. because the cpu16 in the MC68HC16Z1 operates in supervisor mode only, this bit has no effect. adtest ?adc test register $yff702 adtest is used with the sim test register for factory test of the adc. port a is an input port that shares pins with the a/d converter inputs. portada [7:0] a read of portada[7:0] returns the logic level of the port a pins. if the input is not an appropriate volt- age (outside the defined levels), the read will be indeterminate. use of a port a pin for digital input does not preclude its use as an analog input. use adctl0 to select adc clock source and to set up prescaling. writes to it have immediate effect. res10 ?10-bit resolution 0 = 8-bit conversion 1 = 10-bit conversion conversion results are appropriately aligned in result registers to reflect conversion status. frz response 00 ignore ifreeze 01 reserved 10 finish conversion, then freeze 11 freeze immediately portada ?port ada data register $yff706 15 11 10 9 8 7 0 not used portada reset: 0 0 0 0 0 0 0 0 input data adctl0 ?a/d control register 0 $yff70a 15 8 7 6 5 4 3 2 1 0 not used res10 sts prs reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 75 sts[1:0] ?sample time select field total conversion time depends on initial sample time, transfer time, final sample time, and resolution time. initial sample time is fixed at two clocks. transfer time is fixed at two clocks. resolution time is fixed at 10 adc clock cycles for an 8-bit conversion and 12 adc clock cycles for a 10-bit conversion. final sample time is determined by the value in the sts field, as shown in the following table. prs[4:0] ?prescaler rate selection field adc clock is generated from system clock using a modulo counter and a divide-by-two circuit. the bi- nary value of this field is the counter modulus. system clock is divided by the prs value plus one, then sent to the divide-by-two circuit, as shown in the following table. use adctl1 to initiate a/d conversion, or to select conversion modes and conversion channel. it can be written or read at any time. a write to adctl1 initiates a conversion sequence. if a conversion se- quence is already in progress, a write to adctl1 aborts it and resets the scf and ccf flags in the a/ d status register. scan ?scan mode selection bit 0 = single conversion sequence 1 = continuous conversion length of conversion sequence(s) is determined by s8cm. mult ?multichannel conversion bit 0 = conversion sequence(s) run on single channel (channel selected by [cd:ca]) 1 = sequential conversion of a block of four or eight channels (block selected by [cd:ca]) length of conversion sequence(s) is determined by s8cm. s8cm ?select eight-conversion sequence mode 0 = four-conversion sequence 1 = eight-conversion sequence this bit determines the number of conversions in a conversion sequence. [cd:ca] ?channel selection field use the bits in this field to select an input or block of inputs for a/d conversion. sts[1:0] final sample time 00 2 a/d clock periods 01 4 a/d clock periods 10 8 a/d clock periods 11 16 a/d clock periods prs[4:0] divisor value max. system clock min. system clock 00000 reserved 00001 4 8 mhz 2 mhz 00010 6 12 mhz 3 mhz ... ... ... ... 11101 60 120 mhz 30 mhz 11110 62 124 mhz 31 mhz 11111 64 128 mhz 32 mhz adctl1 ?a/d control register 1 $yff70c 15 8 7 6 5 4 3 2 1 0 not used scan mult s8cm cd cc cb ca reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 76 MC68HC16Z1ts/d the following table is a summary of the operation of s8cm and [cd:ca] when mult is cleared (single- channel mode). number of conversions per channel is determined by scan. s8cm cd cc cb ca input result register 0 0000 an0 rslt[0:3] 0 0001 an1 rslt[0:3] 0 0010 an2 rslt[0:3] 0 0011 an3 rslt[0:3] 0 0100 an4 rslt[0:3] 0 0101 an5 rslt[0:3] 0 0110 an6 rslt[0:3] 0 0111 an7 rslt[0:3] 0 1000 reserved rslt[0:3] 0 1001 reserved rslt[0:3] 0 1010 reserved rslt[0:3] 0 1011 reserved rslt[0:3] 0 1100 v rh rslt[0:3] 0 1101 v rl rslt[0:3] 0 1110 (v rh ? v rl ) / 2 rslt[0:3] 0 1111 test/reserved rslt[0:3] 1 0000 an0 rslt[0:7] 1 0001 an1 rslt[0:7] 1 0010 an2 rslt[0:7] 1 0011 an3 rslt[0:7] 1 0100 an4 rslt[0:7] 1 0101 an5 rslt[0:7] 1 0110 an6 rslt[0:7] 1 0111 an7 rslt[0:7] 1 1000 reserved rslt[0:7] 1 1001 reserved rslt[0:7] 1 1010 reserved rslt[0:7] 1 1011 reserved rslt[0:7] 1 1100 v rh rslt[0:7] 1 1101 v rl rslt[0:7] 1 1110 (v rh ? v rl ) / 2 rslt[0:7] 1 1111 test/reserved rslt[0:7] .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 77 the following table is a summary of the operation of s8cm and [cd:ca] when mult is set (multi-chan- nel mode). number of conversions per channel is determined by scan. channel numbers are given in order of conversion. s8cm cd cc cb ca input result register 0 0 0 x x an0 rslt0 an1 rslt1 an2 rslt2 an3 rslt3 0 0 1 x x an4 rslt0 an5 rslt1 an6 rslt2 an7 rslt3 0 1 0 x x reserved rslt0 reserved rslt1 reserved rslt2 reserved rslt3 011xxv rh rslt0 v rl rslt1 (v rh ? v rl ) / 2 rslt2 test/reserved rslt3 1 0 x x x an0 rslt0 an1 rslt1 an2 rslt2 an3 rslt3 an4 rslt4 an5 rslt5 an6 rslt6 an7 rslt7 1 1 x x x reserved rslt0 reserved rslt1 reserved rslt2 reserved rslt3 v rh rslt4 v rl rslt5 (v rh ? v rl ) / 2 rslt6 test/reserved rslt7 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 78 MC68HC16Z1ts/d adstat contains information related to the status of a conversion sequence. scf ?sequence complete flag 0 = sequence not complete 1 = sequence complete scf is set at the end of the conversion sequence when scan is cleared, and at the end of the first conversion sequence when scan is set. scf is cleared when adctl1 is written and a new conversion sequence begins. cctr[2:0] ?conversion counter field this field reflects the contents of the conversion counter pointer in either four or eight count conversion sequence. the value corresponds to the number of the next result register to be written, and thus indi- cates which channel is being converted. ccf[7:0] ?conversion complete field each bit in this field corresponds to an a/d result register (ccf7 to rslt7, etc.). a bit is set when con- version for the corresponding channel is complete, and remains set until the result register is read. a bit is cleared when the register is read. rslt[0:7] ?a/d result registers $yff710?yff73e the result registers store data after conversion is complete. each register can be read from three dif- ferent addresses in the register block. data format depends on the address from which the data is read. rjurr ?unsigned right-justified format $yff710?yff71e conversion result is unsigned right-justified data. bits [9:0] are used for 10-bit resolution, bits [7:0] are used for 8-bit conversion (bits [9:8] are zero). bits [15:10] always return zero when read. ljsrr ?signed left-justified format $yff720?yff72e conversion result is signed left-justified data. bits [15:6] are used for 10-bit resolution, and bits [15:8] are used for 8-bit conversion (bits [7:6] are zero). although the adc is unipolar, it is assumed that the zero point is halfway between low and high reference when this format is used. for positive input, bit 15 = 0. for negative input, bit 15 = 1. bits [5:0] always return zero when read. ljurr ?unsigned left-justified format $yff730?yff73e conversion result is unsigned left-justified data. bits [15:6] are used for 10-bit resolution, and bits [15:8] are used for 8-bit conversion (bits [7:6] are zero). bits [5:0] always return zero when read. adstat ?adc status register $yff70e 15 14 11 10 8 7 0 scf not used cctr ccf reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 79 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 80 MC68HC16Z1ts/d 5 queued serial module the qsm contains two serial interfaces, the queued serial peripheral interface (qspi) and the serial communication interface (sci). the qspi provides easy peripheral expansion or interprocessor communication through a full-duplex, synchronous, three-line bus: data in, data out, and a serial clock. four programmable peripheral-select pins provide addressability for up to 16 peripheral devices. a self-contained ram queue allows up to 16 serial transfers of 8?6 bits each, or transmission of a 256-bit data stream without cpu intervention. a special wraparound mode supports continuous sampling of a serial peripheral, with automatic qspi ram updating, which makes the interface to a/d converters more efficient. the sci provides a standard nonreturn to zero (nrz) mark/space format. it operates in either full- or half-duplex mode. there are separate transmitter and receiver enable bits and dual data buffers. a modulus-type baud rate generator provides rates from 64 to 524 kbaud with a 16.78-mhz system clock. word length of either 8 or 9 bits is software selectable. optional parity generation and detection provide either even or odd parity check capability. advanced error detection circuitry catches glitches of up to 1/16 of a bit time in duration. wake-up functions allow the cpu to run uninterrupted until meaningful data is available. refer to the following block diagram of the qsm. figure 14 qsm block diagram qspi interface logic sci pqs0/miso pqs1/mosi pqs2/sck pqs3/ss /pcs0 pqs4/pcs1 pqs5/pcs2 pqs6/pcs3 pqs7/txd rxd port qs qsm block imb .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 81 y = m111, where m is the logic state of the modmap (mm) bit in the simcr the following table is a summary of the functions of the qsm pins when they are not configured for gen- eral-purpose i/o. the qsm data direction register (ddrqs) designates each pin (except rxd) as input or output. 5.1 qsm registers there are four types of qsm registers: qsm global registers, qsm pin control registers, qspi submod- ule registers, and sci submodule registers. the qspi and sci registers are defined in separate sec- tions below. writes to unimplemented register bits have no meaning or effect, and reads from unimplemented bits always return a logic zero value. table 18 qsm address map address 15 8 7 0 $yffc00 qsm module configuration (qsmcr) $yffc02 qsm test (qtest) $yffc04 qsm interrupt level (qilr) qsm interrupt vector (qivr) $yffc06 reserved $yffc08 sci control 0 (sccr0) $yffc0a sci control 1 (sccr1) $yffc0c sci status (scsr) $yffc0e sci data (scdr) $yffc10 reserved $yffc12 reserved $yffc14 reserved pqs data (portqs) $yffc16 pqs pin assignment (pqspar) pqs data direction (ddrqs) $yffc18 spi control 0 (spcr0) $yffc1a spi control 1 (spcr1) $yffc1c spi control 2 (spcr2) $yffc1e spi control 3 (spcr3) spi status (spsr) $yffc20 $yffcff reserved $yffd00 $yffd1f receive ram (rr[0:f]) $yffd20 $yffd3f transmit ram (tr[0:f]) $yffd40 $yffd4f command ram (cr[0:f]) qspi pins pin mode pin function miso master serial data input to qspi slave serial data output from qspi mosi master serial data output from qspi slave serial data input to qspi sck master clock output from qspi slave clock input to qspi pcs0/ss master input: assertion causes mode fault output: selects peripherals slave input: selects the qspi pcs[3:1] master output: selects peripherals slave none sci pins txd transmit serial data output from sci rxd receive serial data input to sci .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 82 MC68HC16Z1ts/d the modmap (mm) bit in the system integration module configuration register (simcr) defines the most significant bit (addr23) of the address, shown in each register figure as y. this bit, concatenated with the rest of the address given, forms the absolute address of each register. because the cpu16 in the MC68HC16Z1 drives only addr[19:0], addr[23:20] follow the logic state of addr19, and y must equal $f. refer to the sim section of this technical summary for more information about how the state of mm affects the system. 5.1.1 global registers the qsm global registers contain system parameters used by both the qspi and the sci submodules. these registers contain the bits and fields used to configure the qsm. the qsmcr contains parameters for the qsm/cpu/intermodule bus (imb) interface. stop ?stop enable 0 = normal qsm clock operation 1 = qsm clock operation stopped stop places the qsm in a low-power state by disabling the system clock in most parts of the module. qsmcr is the only register guaranteed to be readable while stop is asserted. the qspi ram is not readable. however, writes to ram or any register are guaranteed to be valid while stop is asserted. stop can be negated by the cpu and by reset. the system software must stop each submodule before asserting stop to avoid complications at re- start and to avoid data corruption. the sci submodule receiver and transmitter should be disabled, and the operation should be verified for completion before asserting stop. the qspi submodule should be stopped by asserting the halt bit in spcr3 and by asserting stop after the halta flag is set. frz1 ?freeze 1 0 = ignore the freeze signal on the imb 1 = halt the qspi (on a transfer boundary) frz1 determines what action is taken by the qspi when the freeze signal of the imb is asserted. freeze is asserted whenever the cpu enters the background mode. frz0 ?freeze 0 reserved bits [12:8] ?not implemented supv ?supervisor/unrestricted 0 = user access 1 = supervisor access (MC68HC16Z1 default) supv defines the assignable qsm registers as either supervisor-only data space or unrestricted data space. because the cpu16 in the MC68HC16Z1 operates in supervisor mode only, this bit has no ef- fect. bits [6:4] ?not implemented iarb ?interrupt arbitration identification number each module that generates interrupts must have an iarb field. in this field, each module has a unique value that is used to arbitrate for the imb when modules generate simultaneous interrupts of the same priority. refer to the sim section of this summary for more information. qsmcr ?qsm configuration register $yffc00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stop frz1 frz0 0 0 0 0 0 supv 0 0 0 iarb reset: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 83 qtest ?qsm test register $yffc02 qtest is used during factory test of the qsm. accesses to qtest must be made while the mcu is in test mode. qilr determines the priority level of interrupts requested by the qsm and the vector used when an in- terrupt is acknowledged. ilqspi ?interrupt level for qspi ilqspi determines the priority of qspi interrupts. this field must be given a value between $0 (inter- rupts disabled) to $7 (highest priority). ilsci ?interrupt level of sci ilsci determines the priority of sci interrupts. this field must be given a value between $0 (interrupts disabled) to $7 (highest priority). if ilqspi and ilsci are the same (nonzero) value, and both submodules simultaneously request inter- rupt service, qspi has priority. at reset, qivr is initialized to $0f, which corresponds to the uninitialized interrupt vector in the excep- tion table. this vector is selected until qivr is written. a user-defined vector ($40?ff) should be writ- ten to qivr during qsm initialization. after initialization, qivr determines which two vectors in the exception vector table are to be used for qsm interrupts. the qspi and sci submodules have separate interrupt vectors adjacent to each other. both submodules use the same interrupt vector with the least significant bit (lsb) determined by the submodule causing the interrupt. the value of intv0 used during an iack cycle is supplied by the qsm. during an iack, intv[7:1] are driven on data[7:1] imb lines. data0 is negated for an sci interrupt and asserted for a qspi interrupt. writes to intv0 have no meaning or effect. reads of intv0 return a value of one. 5.1.2 pin control registers the qsm uses nine pins, eight of which form a parallel port (portqs) on the mcu. although these pins are used by the serial subsystems, any pin can alternately be assigned as general-purpose input/ output (i/o) on a pin-by-pin basis. pins used for general-purpose i/o must not be assigned to the qspi by register pqspar. to avoid driving incorrect data, the first byte to be output must be written before ddrqs is configured. ddrqs must then be written to determine the direction of data flow and to output the value contained in register portqs. subsequent data for output is written to portqs. qilr ?qsm interrupt levels register $yffc04 15 14 13 12 11 10 9 8 8 0 0 0 ilqspi ilsci qivr reset: 0 0 0 0 0 0 0 0 qivr ?qsm interrupt vector register $yffc05 15 8 7 6 5 4 3 2 1 0 qilr intv reset: 0 0 0 0 1 1 1 1 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 84 MC68HC16Z1ts/d portqs is the port qs data register. writes to portqs affect pins defined as outputs. reads of portqs return data present on the pins. pqspar determines whether certain pins are used by the qspi submodule, or whether they are avail- able for general-purpose i/o. pins designated for general-purpose i/o are controlled by ddrqs and portqs. pqspar does not affect operation of the sci submodule. bits 15 and 10 are not implement- ed. pcs[3:1] ?peripheral chip selects pcs0/ss ?peripheral chip select 0/slave select mosi ?master out slave in miso ?master in slave out 0 = used for general-purpose i/o 1 = used by qspi submodule ddrqs determines whether a general-purpose i/o pin is an input or an output. during reset, all qsm pins are configured as general-purpose inputs. txd ?transmit data 0 = input 1 = output this bit determines the direction of the txd pin only when the sci transmitter is disabled. when the sci transmitter is enabled, the txd pin is an output. all of the following bits determine the corresponding qspi port pin operation to be input or output. pcs[3:1] ?peripheral chip selects pcs0/ss ?peripheral chip select 0/slave select sck ?serial clock mosi ?master out slave in miso ?master in slave out 0 = input 1 = output portqs ?port qs data register $yffc15 15 8 7 6 5 4 3 2 1 0 reserved data7 (txd) data6 (pcs3) data5 (pcs2) data4 (pcs1) data3 (pcs0/ ss ) data2 (sck) data1 (mosi) data0 (miso) reset: 0 0 0 0 0 0 0 0 pqspar ?port qs pin assignment register $yffc16 15 14 13 12 11 10 9 8 7 0 0 pcs3 pcs2 pcs1 pcs0/ ss 0 mosi miso ddrqs reset: 0 0 0 0 0 0 0 0 ddrqs ?port qs data direction register $yffc17 15 8 7 6 5 4 3 2 1 0 pqspar txd pcs3 pcs2 pcs1 pcs0/ ss sck mosi miso reset: 0 0 0 0 0 0 0 0 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 85 5.2 qspi submodule the qspi submodule communicates with external devices through a synchronous serial bus. the qspi is fully compatible with the serial peripheral interface (spi) systems found on other motorola products. refer to the following block diagram of the qspi. figure 15 qspi block diagram 5.2.1 qspi pins seven pins are associated with the qspi. when not needed for a qspi application, they can be con- figured as general-purpose i/o pins. refer to the following table for qspi input and output pins and their functions. qspi block control registers end queue pointer queue pointer status register delay counter comparator programmable logic array 80-byte qspi ram chip select command done 4 4 3 baud rate generator pcs [3:1] pcs0/ss miso mosi sck m s m s 8/16-bit shift register rx/tx data register msb lsb 4 queue control block control logic address register 4 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 86 MC68HC16Z1ts/d 5.2.2 qspi registers the programmer's model for the qspi submodule consists of the qsm global and pin control registers, four qspi control registers, one status register, and the 80-byte qspi ram. registers and ram can be read and written by the cpu. the four control registers must be initialized before the qspi is enabled to insure defined operation. spcr1 should be written last because it con- tains qspi enable bit spe. asserting this bit starts the qspi. the qspi control registers are reset to a defined state and can then be changed by the cpu. reset values are shown below each register. refer to the following memory map of the qspi. writing a different value into any control register except spcr2 while the qspi is enabled disrupts op- eration. spcr2 is buffered to prevent disruption of the current serial transfer. after completion of the current serial transfer, the new spcr2 values become effective. writing the same value into any control register except spcr2 while the qspi is enabled has no effect on qspi operation. rewriting newqp in spcr2 causes execution to restart at the designated location. spcr0 contains parameters for configuring the qspi before it is enabled. the cpu can read and write this register. the qsm has read-only access. pin names mnemonics mode function master in slave out miso master slave serial data input to qspi serial data output from qspi master out slave in mosi master slave serial data output from qspi serial data input to qspi serial clock sck master slave clock output from qspi clock input to qspi peripheral chip selects pcs[3:0] master select peripherals slave select ss master slave causes mode fault initiates serial transfer address name usage $yffc18 spcr0 qspi control register 0 $yffc1a spcr1 qspi control register 1 $yffc1c spcr2 qspi control register 2 $yffc1e spcr3 qspi control register 3 $yffc1f spsr qspi status register $yffd00 ram qspi receive data (16 words) $yffd20 ram qspi transmit data (16 words) $yffd40 ram qspi command control (8 words) spcr0 ?qspi control register 0 $yffc18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mstr womq bits cpol cpha spbr reset: 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 87 mstr ?master/slave mode select 0 = qspi is a slave device and only responds to externally generated serial data. 1 = qspi is system master and can initiate transmission to external spi devices. mstr configures the qspi for either master or slave mode operation. this bit is cleared on reset and may only be written by the cpu. womq ?wired-or mode for qspi pins 0 = outputs have normal mos drivers. 1 = pins designated for output by ddrqs have open-drain drivers. womq allows the wired-or function to be used on qspi pins, regardless of whether they are used as general-purpose outputs or as qspi outputs. womq affects the qspi pins whether the qspi is en- abled or disabled. bits ?bits per transfer in master mode, when bitse in a command is set, the bits field determines the number of data bits transferred. when bitse is cleared, eight bits are transferred. reserved values default to eight bits. bitse is not used in slave mode. the following table shows the number of bits per transfer. cpol ?clock polarity 0 = the inactive state value of sck is logic level zero. 1 = the inactive state value of sck is logic level one. cpol is used to determine the inactive state value of the serial clock (sck). it is used with cpha to produce a desired clock/data relationship between master and slave devices. cpha ?clock phase 0 = data is captured on the leading edge of sck and changed on the following edge of sck. 1 = data is changed on the leading edge of sck and captured on the following edge of sck. cpha determines which edge of sck causes data to change and which edge causes data to be cap- tured. cpha is used with cpol to produce a desired clock/data relationship between master and slave devices. cpha is set at reset. bits bits per transfer 0000 16 0001 reserved 0010 reserved 0011 reserved 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 88 MC68HC16Z1ts/d spbr ?serial clock baud rate the qspi uses a modulus counter to derive sck baud rate from the mcu system clock. baud rate is selected by writing a value from 2 to 255 into the spbr field. the following equation determines the sck baud rate: sck baud rate = system clock/(2spbr) or spbr = system clock/(2sck)(baud rate desired) where spbr equals {2, 3, 4,..., 255} giving spbr a value of zero or one disables the baud rate generator. sck is disabled and assumes its inactive state value. no serial transfers occur. at reset, baud is initialized to a 2.1-mhz sck frequency. spcr1 contains parameters for configuring the qspi before it is enabled. the cpu can read and write this register, but the qsm has read access only, except for spe, which is automatically cleared by the qspi after completing all serial transfers, or when a mode fault occurs. spe ?qspi enable 0 = qspi is disabled. qspi pins can be used for general-purpose i/o. 1 = qspi is enabled. pins allocated by pqspar are controlled by the qspi. dsckl ?delay before sck when the dsck bit in command ram is set, this field determines the length of delay from pcs valid to sck transition. pcs can be any of the four peripheral chip-select pins. the following equation deter- mines the actual delay before sck: pcs to sck delay = [dsckl/system clock] where dsckl equals {1, 2, 3,..., 127}. when a queue entry's dsck equals zero, then dsckl is not used. instead, the pcs valid-to-sck tran- sition is one-half sck period. dtl ?length of delay after transfer when the dt bit in command ram is set, this field determines the length of delay after serial transfer. the following equation is used to calculate the delay: delay after transfer = [(32dtl)/system clock] where dtl equals {1, 2, 3,..., 255}. a zero value for dtl causes a delay-after-transfer value of 8192/system clock. if dt equals zero, a standard delay is inserted. standard delay after transfer = [17/system clock] delay after transfer can be used to provide a peripheral deselect interval. a delay can also be inserted between consecutive transfers to allow serial a/d converters to complete conversion. spcr1 ?qspi control register 1 $yffc1a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spe dsckl dtl reset: 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 spcr2 ?qspi control register 2 $yffc1c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spifie wren wrto 0 endqp 0 0 0 0 newqp reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 89 spcr2 contains qspi configuration parameters. although the cpu can read and write this register, the qsm has read access only. writes to spcr2 are buffered. a write to spcr2 that changes a bit value while the qspi is operating is ineffective on the current serial transfer, but becomes effective on the next serial transfer. reads of spcr2 return the current value of the register, not of the buffer. spifie ?spi finished interrupt enable 0 = qspi interrupts disabled 1 = qspi interrupts enabled spifie enables the qspi to generate a cpu interrupt upon assertion of the status flag spif. wren ?wrap enable 0 = wraparound mode disabled 1 = wraparound mode enabled wren enables or disables wraparound mode. wrto ?wrap to when wraparound mode is enabled, after the end of queue has been reached, wrto determines which address the qspi executes. bit 12 ?not implemented endqp ?ending queue pointer this field contains the last qspi queue address. bits [7:4] ?not implemented newqp ?new queue pointer value this field contains the first qspi queue address. spcr3 contains qspi configuration parameters. the cpu can read and write spcr3, but the qsm has read-only access. bits [15:11] ?not implemented loopq ?qspi loop mode 0 = feedback path disabled 1 = feedback path enabled loopq controls feedback on the data serializer for testing. hmie ?halta and modf interrupt enable 0 = halta and modf interrupts disabled 1 = halta and modf interrupts enabled hmie controls cpu interrupts caused by the halta status flag or the modf status flag in spsr. halt ?halt 0 = halt not enabled 1 = halt enabled when halt is asserted, the qspi stops on a queue boundary. it is in a defined state from which it can later be restarted. spcr3 ?qspi control register 3 $yffc1e 15 14 13 12 11 10 9 8 7 0 0 0 0 0 0 loopq hmie halt spsr reset: 0 0 0 0 0 0 0 0 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 90 MC68HC16Z1ts/d spsr contains qspi status information. only the qspi can assert the bits in this register. the cpu reads this register to obtain status information and writes it to clear status flags. spif ?qspi finished flag 0 = qspi not finished 1 = qspi finished spif is set after execution of the command at the address in endqp. modf ?mode fault flag 0 = normal operation 1 = another spi node requested to become the network spi master while the qspi was enabled in master mode (ss input taken low). modf is asserted by the qspi when the qspi is the serial master (mstr = 1) and the ss input pin is negated by an external driver. halta ?halt acknowledge flag 0 = qspi not halted 1 = qspi halted halta is asserted when the qspi halts in response to cpu assertion of halt. bit 4 ?not implemented cptqp ?completed queue pointer cptqp points to the last command executed. it is updated when the current command is complete. when the first command in a queue is executing, cptqp contains either the reset value ($0) or a point- er to the last command completed in the previous queue. 5.2.3 qspi ram the qspi contains an 80-byte block of dual-access static ram that is used by both the qspi and the cpu. the ram is divided into three segments: receive data ram, transmit data ram, and command control ram. receive data is information received from a serial device external to the mcu. transmit data is information stored by the cpu for transmission to an external peripheral. command control data is used to perform the transfer. refer to the following illustration of the organization of the ram. spsr ?qspi status register $yffc1f 15 8 7 6 5 4 3 2 1 0 spcr3 spif modf halta 0 cptqp reset: 0 0 0 0 0 0 0 0 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 91 figure 16 qspi ram address map once the cpu has set up the queue of qspi commands and enabled the qspi, the qspi can operate independently of the cpu. the qspi executes all of the commands in its queue, sets a flag indicating that it is finished, and then either interrupts the cpu or waits for cpu intervention. it is possible to ex- ecute a queue of commands repeatedly without cpu intervention. rr[0:f] ?receive data ram $yffd00 data received by the qspi is stored in this segment. the cpu reads this segment to retrieve data from the qspi. data stored in receive ram is right-justified. unused bits in a receive queue entry are set to zero by the qspi upon completion of the individual queue entry. the cpu can access the data using byte, word, or long-word addressing. the cptqp value in spsr shows which queue entries have been executed. the cpu uses this infor- mation to determine which locations in receive ram contain valid data before reading them. tr[0:f] ?transmit data ram $yffd20 data that is to be transmitted by the qspi is stored in this segment. the cpu usually writes one word of data into this segment for each queue command to be executed. information to be transmitted must be written to transmit data ram in a right-justified format. the qspi cannot modify information in the transmit data ram. the qspi copies the information to its data serial- izer for transmission. information remains in transmit ram until overwritten. *the pcs0 bit represents the dual-function pcs0/ss . command ram consists of 16 bytes that are divided into two fields. the peripheral chip-select field en- ables peripherals for transfer. the command control field provides transfer options. command ram is used by the qspi when in master mode. the cpu writes one byte of control information to this segment for each qspi command to be executed. the qspi cannot modify information in command ram. a cr[0:f] ?command ram $yffd40 7 6 5 4 3 2 1 0 cont bitse dt dsck pcs3 pcs2 pcs1 pcs0 * ? ? ? ? ? ? ? ? cont bitse dt dsck pcs3 pcs2 pcs1 pcs0* command control peripheral chip select qspi ram map receive ram transmit ram d00 d1e d20 d3e word d40 d4f command ram byte word rr0 rr1 rr2 rrd rre rrf tr0 tr1 tr2 trd tre trf cr0 cr1 cr2 crd cre crf .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 92 MC68HC16Z1ts/d maximum of 16 commands can be in the queue. queue execution by the qspi proceeds from the ad- dress in newqp through the address in endqp (both of these fields are in spcr2). cont ?continue 0 = control of chip selects returned to portqs after transfer is complete. 1 = peripheral chip selects remain asserted after transfer is complete. bitse ?bits per transfer enable 0 = 8 bits 1 = number of bits set in bits field of spcr0 dt ?delay after transfer the qspi provides a variable delay at the end of serial transfer to facilitate the interface with peripherals that have a latency requirement. the delay between transfers is determined by the spcr1 dtl field. dsck ?pcs to sck delay 0 = pcs valid to sck transition is one-half sck. 1 = spcr1 dsckl field specifies delay from pcs valid to sck. pcs[3:0] ?peripheral chip select use peripheral chip-select bits to select an external for serial data transfer. more than one peripheral chip select can be activated at a time, and more than one peripheral chip can be connected to each pcs pin, provided that proper fanout is observed. ss ?slave mode select initiates slave mode serial transfer. if ss is taken low when the qspi is in master mode, a mode fault will be generated. 5.2.4 operating modes the qspi operates in either master or slave mode. master mode is used when the mcu originates data transfers. slave mode is used when an external device initiates serial transfers to the mcu through the qspi. switching between the modes is controlled by mstr in spcr0. before entering either mode, appropriate qsm and qspi registers must be properly initialized. in master mode, the qspi executes a queue of commands defined by control bits in each command ram queue entry. chip-select pins are activated, data is transmitted from transmit data ram and re- ceived into receive data ram. in slave mode, operation proceeds in response to ss pin activation by an external bus master. opera- tion is similar to master mode, but no peripheral chip selects are generated, and the number of bits transferred is controlled in a different manner. when the qspi is selected, it automatically executes the next queue transfer to exchange data with the external device correctly. although the qspi inherently supports multimaster operation, no special arbitration mechanism is pro- vided. a mode fault flag (modf) indicates a request for spi master arbitration. system software must provide arbitration. note that unlike previous spi systems, mstr is not cleared by a mode fault being set, nor are the qspi pin output drivers disabled. the qspi and associated output drivers must be dis- abled by clearing spe in spcr1. 5.3 sci submodule the sci submodule is used to communicate with external devices through an asynchronous serial bus. the sci is fully compatible with the sci systems found on other motorola mcus, such as the m68hc11 and m68hc05 families. .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 93 5.3.1 sci pins there are two unidirectional pins associated with the sci. the sci controls the transmit data (txd) pin when enabled, whereas the receive data (rxd) pin remains a dedicated input pin to the sci. txd is available as a general-purpose i/o pin when the sci transmitter is disabled. when used for i/o, txd can be configured either as input or output, as determined by qsm register ddrqs. the following table shows sci pins and their functions. 5.3.2 sci registers the sci programming model includes qsm global and pin control registers, and four sci registers. there are two sci control registers, one status register, and one data register. all registers can be read or written at any time by the cpu. changing the value of sci control bits during a transfer operation may disrupt operation. before chang- ing register values, allow the transmitter to complete the current transfer, then disable the receiver and transmitter. status flags in register scsr may be cleared at any time. sccr0 contains a baud rate selection parameter. baud rate must be set before the sci is enabled. the cpu can read and write this register at any time. bits [15:13] ?not implemented scbr ?baud rate sci baud rate is programmed by writing a 13-bit value to scbr. the baud rate is derived from the mcu system clock by a modulus counter. the sci receiver operates asynchronously. an internal clock is necessary to synchronize with an in- coming data stream. the sci baud rate generator produces a receiver sampling clock with a frequency 16 times that of the expected baud rate of the incoming data. the sci determines the position of bit boundaries from transitions within the received waveform, and adjusts sampling points to the proper po- sitions within the bit period. receiver sampling rate is always 16 times the frequency of the sci baud rate, which is calculated as follows: sci baud rate = system clock/(32scbr) or scbr = system clock(32sck)(baud rate desired) where scbr is in the range {1, 2, 3, ..., 8191} writing a value of zero to br disables the baud rate generator. pin names mnemonics mode function receive data rxd receiver disabled receiver enabled not used serial data input to sci transmit data txd transmitter disabled transmitter enabled general-purpose i/o serial data output from sci sccr0 ?sci control register 0 $yffc08 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 scbr reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 94 MC68HC16Z1ts/d sccr1 contains sci configuration parameters. the cpu can read and write this register at any time. the sci can modify rwu in some circumstances. in general, interrupts enabled by these control bits are cleared by reading scsr, then reading (receiver status bits) or writing (transmitter status bits) scdr. bit 15 ?not implemented loops ?loop mode 0 = normal sci operation, no looping, feedback path disabled 1 = test sci operation, looping, feedback path enabled loops controls a feedback path on the data serial shifter. when loop mode is enabled, sci transmitter output is fed back into the receive serial shifter. txd is asserted (idle line). both transmitter and receiver must be enabled before entering loop mode. woms ?wired-or mode for sci pins 0 = if configured as an output, txd is a normal cmos output. 1 = if configured as an output, txd is an open-drain output. woms determines whether the txd pin is an open-drain output or a normal cmos output. this bit is used only when txd is an output. if txd is used as a general-purpose input pin, woms has no effect. ilt ?idle-line detect type 0 = short idle-line detect (start count on first one) 1 = long idle-line detect (start count on first one after stop bit(s)) pt ?parity type 0 = even parity 1 = odd parity when parity is enabled, pt determines whether parity is even or odd for both the receiver and the trans- mitter. pe ?parity enable 0 = sci parity disabled 1 = sci parity enabled pe determines whether parity is enabled or disabled for both the receiver and the transmitter. if the re- ceived parity bit is not correct, the sci sets the pf error flag in scsr. when pe is set, the most significant bit (msb) of the data field is used for the parity function, which re- sults in either seven or eight bits of user data, depending on the condition of m bit. the following table lists the available choices. m ?mode select 0 = sci frame: 1 start bit, 8 data bits, 1 stop bit (10 bits total) 1 = sci frame: 1 start bit, 9 data bits, 1 stop bit (11 bits total) sccr1 ?sci control register 1 $yffc0a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 loops woms ilt pt pe m wake tie tcie rie ilie te re rwu sbk reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 m pe result 0 0 8 data bits 0 1 7 data bits, 1 parity bit 1 0 9 data bits 1 1 8 data bits, 1 parity bit .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 95 wake ?wake-up by address mark 0 = sci receiver awakened by idle-line detection 1 = sci receiver awakened by address mark (last bit set) tie ?transmit interrupt enable 0 = sci tdre interrupts inhibited 1 = sci tdre interrupts enabled tcie ?transmit complete interrupt enable 0 = sci tc interrupts inhibited 1 = sci tc interrupts enabled rie ?receiver interrupt enable 0 = sci rdrf interrupt inhibited 1 = sci rdrf interrupt enabled ilie ?idle-line interrupt enable 0 = sci idle interrupts inhibited 1 = sci idle interrupts enabled te ?transmitter enable 0 = sci transmitter disabled (txd pin may be used as i/o) 1 = sci transmitter enabled (txd pin dedicated to sci transmitter) the transmitter retains control of the txd pin until completion of any character transfer that was in progress when te is cleared. re ?receiver enable 0 = sci receiver disabled (status bits inhibited) 1 = sci receiver enabled rwu ?receiver wakeup 0 = normal receiver operation (received data recognized) 1 = wakeup mode enabled (received data ignored until awakened) setting rwu enables the wakeup function, which allows the sci to ignore received data until awakened by either an idle line or address mark (as determined by wake). when in wakeup mode, the receiver status flags are not set, and interrupts are inhibited. this bit is cleared automatically (returned to normal mode) when the receiver is awakened. sbk ?send break 0 = normal operation 1 = break frame(s) transmitted after completion of current frame sbk provides the ability to transmit a break code from the sci. if the sci is transmitting when sbk is set, it will transmit continuous frames of zeros after it completes the current frame, until sbk is cleared. if sbk is toggled (one to zero in less than one frame interval), the transmitter sends only one or two break frames before reverting to idle line or beginning to send data. scsr contains flags that show sci operational conditions. these flags can be cleared either by hard- ware or by a special acknowledgment sequence. the sequence consists of scsr read with flags set, followed by scdr read (write in the case of tdre and tc). a long-word read can consecutively access both scsr and scdr. this action clears receive status flag bits that were set at the time of the read, but does not clear tdre or tc flags. scsr ?sci status register $yffc0c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used tdre tc rdrf raf idle or nf fe pf reset: 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 96 MC68HC16Z1ts/d if an internal sci signal for setting a status bit comes after the cpu has read the asserted status bits, but before the cpu has written or read register scdr, the newly set status bit is not cleared. scsr must be read again with the bit set. also, scdr must be written or read before the status bit is cleared. reading either byte of scsr causes all 16 bits to be accessed. any status bit already set in either byte will be cleared on a subsequent read or write of register scdr. tdre ?transmit data register empty flag 0 = register tdr still contains data to be sent to the transmit serial shifter. 1 = a new character can now be written to register tdr. tdre is set when the byte in register tdr is transferred to the transmit serial shifter. if tdre is zero, transfer has not occurred and a write to tdr will overwrite the previous value. new data is not trans- mitted if tdr is written without first clearing tdre. tc ?transmit complete flag 0 = sci transmitter is busy 1 = sci transmitter is idle tc is set when the transmitter finishes shifting out all data, queued preambles (mark/idle line), or queued breaks (logic zero). the interrupt can be cleared by reading scsr when tc is set and then by writing the transmit data register (tdr) of scdr. rdrf ?receive data register full flag 0 = register rdr is empty or contains previously read data. 1 = register rdr contains new data. rdrf is set when the content of the receive serial shifter is transferred to the rdr. if one or more errors are detected in the received word, flag(s) nf, fe, and/or pf are set within the same clock cycle. raf ?receiver active flag 0 = sci receiver is idle 1 = sci receiver is busy raf indicates whether the sci receiver is busy. it is set when the receiver detects a possible start bit and is cleared when the chosen type of idle line is detected. raf can be used to reduce collisions in systems with multiple masters. idle ?idle-line detected flag 0 = sci receiver did not detect an idle-line condition. 1 = sci receiver detected an idle-line condition. idle is disabled when rwu in sccr1 is set. idle is set when the sci receiver detects the idle-line condition specified by ilt in sccr1. if cleared, idle will not set again until after rdrf is set. rdrf is set when a break is received, so that a subsequent idle line can be detected. or ?overrun error flag 0 = rdrf is cleared before new data arrives. 1 = rdrf is not cleared before new data arrives. or is set when a new byte is ready to be transferred from the receive serial shifter to the rdr, and rdrf is still set. data transfer is inhibited until or is cleared. previous data in rdr remains valid, but data received during overrun condition (including the byte that set or) is lost. nf ?noise error flag 0 = no noise detected on the received data 1 = noise occurred on the received data nf is set when the sci receiver detects noise on a valid start bit, on any data bit, or on a stop bit. it is not set by noise on the idle line or on invalid start bits. each bit is sampled three times. if none of the three samples are the same logic level, the majority value is used for the received data value, and nf is set. nf is not set until an entire frame is received and rdrf is set. .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 97 fe ?framing error flag 1 = framing error or break occurred on the received data. 0 = no framing error on the received data. fe is set when the sci receiver detects a zero where a stop bit was to have occurred. fe is not set until the entire frame is received and rdrf is set. a break can also cause fe to be set. it is possible to miss a framing error if rxd happens to be at logic level one at the time the stop bit is expected. pf ?parity error flag 1 = parity error occurred on the received data 0 = no parity error on the received data pf is set when the sci receiver detects a parity error. pf is not set until the entire frame is received and rdrf is set. scdr contains two data registers at the same address. rdr is a read-only register that contains data received by the sci serial interface. the data comes into the receive serial shifter and is transferred to rdr. tdr is a write-only register that contains data to be transmitted. the data is first written to tdr, then transferred to the transmit serial shifter, where additional format bits are added before transmis- sion. r[7:0]/t[7:0] contain either the first eight data bits received when scdr is read, or the first eight data bits to be transmitted when scdr is written. r8/t8 are used when the sci is configured for 9-bit operation. when it is configured for 8-bit operation, they have no meaning or effect. scdr ?sci data register $yffc0e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 r8/t8 r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 reset: 0 0 0 0 0 0 0 u u u u u u u u u .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 98 MC68HC16Z1ts/d .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 99 6 standby ram module this module contains a one kbyte array of fast (two bus cycle) static ram, which is especially useful for system stacks and variable storage. sram can be mapped to any one kbyte boundary in the ad- dress map, but must not overlap the module control registers (overlap makes the registers inaccessi- ble). data can be read/written in bytes, words or long words. sram is powered by v dd in normal operation. during power-down, sram contents are maintained by power from the v stby input. power switching between sources is automatic. an address map of the sram control registers follows. y = m111, where m is the logic state of the modmap (mm) bit in the simcr 6.1 sram register block there are four sram control registers: the ram module configuration register (rammcr), the ram test register (ramtst), and the ram array base address registers (rambah/rambal). there is an 8-byte minimum register block size for the module. unimplemented register addresses are read as zeros. writes have no effect. 6.2 sram registers the cpu16 in the MC68HC16Z1 operates only in supervisory mode. access to the sram array is con- trolled by the rasp field in rammcr. sram responds to both program and data space accesses based on the value in the rasp field in rammcr. this allows code to be executed from ram, and permits the use of program counter relative addressing mode for operand fetches from the array. use rammcr to determine whether the ram is in stop mode or normal mode. it can also determine in which space the array resides, and controls access to the base array registers. reads of unimple- mented bits always return zeros. writes do not affect unimplemented bits. stop ?stop control 0 = ram array operates normally. 1 = ram array enters low-power stop mode. this bit controls whether the ram array is in stop mode or normal operation. reset state is one, leaving the array configured for lpstop operation. in stop mode, the array retains its contents, but cannot be read or written by the cpu. because the cpu16 operates in supervisor mode, this bit can be read or written at any time. rlck ?ram base address lock 0 = sram base address registers are writable from imb 1 = sram base address registers are locked rlck defaults to zero on reset. it can be written to one once. table 19 sram address map address 15 8 7 0 $yffb00 ram module configuration register (rammcr) $yffb02 ram test register (ramtst) $yffb04 ram array base address register high (rambah) $yffb06 ram array base address register low (rambal) $yffb08 reserved rammcr ?ram module configuration register $yffb00 15 11 9 8 7 6 5 4 3 2 1 0 stop 0 0 0 rlck 0 rasp not used reset: 1 0 0 0 0 0 1 1 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 100 MC68HC16Z1ts/d rasp[1:0] ?ram array space field this field limits access to the sram array in microcontrollers that support separate user and supervisor operating modes. because the cpu16 operates in supervisor mode only, rasp1 has no effect. ramtst ?ram test register $yffb02 ramtst is for factory test only. reads of this register return zeros and writes have no effect. *addr[23:20] is at the same logic level as addr19 during internal cpu master operation. addr[23:20] must match addr19 for the chip select to be active. rambah and rambal specify an sram base address in the system memory map. they can only be written while the sram is in low-power mode (rammcr stop = 1, the default out of reset) and the base address lock is disabled (rammcr rlck = 0, the default out of reset). this prevents accidental remapping of the array. because the cpu16 drives addr[23:20] with the value of addr19, the value in the addr[23:20] fields must match the value in the addr19 field for the array to be accessible. 6.3 sram operation there are five operating modes. the ram module is in normal mode when powered by v dd . the array can be accessed by byte, word, or long word. a byte or aligned word (high-order byte is at an even address) access only takes one bus cycle or two system clocks. a long word or misaligned word access requires two bus cycles. standby mode is intended to preserve ram contents when v dd is removed. sram contents are main- tained by a power source connected to the v stby pin. the standby voltage is referred to as v sb . cir- cuitry within the sram module switches to the higher of v dd or v sb with no loss of data. when sram is powered from the v stby pin, access to the array is not guaranteed. if standby operation is not desired, connect the v stby pin to v ss . reset mode allows the cpu to complete the current bus cycle before resetting. when a synchronous reset occurs while a byte or word sram access is in progress, the access will be completed. if reset occurs during the first word access of a long-word operation, only the first word access will be complet- ed. if reset occurs during the second word access of a long word operation, the entire access will be completed. data being read from or written to the ram may be corrupted by asynchronous reset. test mode is used for factory testing of the ram array. writing the stop bit of rammcr causes the sram module to enter stop mode. the ram array is dis- abled which, if necessary, allows external logic to decode sram addresses but all data is retained. if v dd falls below v sb , internal circuitry switches to v sb , as in standby mode. exit the stop mode by clear- ing the stop bit. rasp space x0 program and data x1 program rambah ?array base address register high $yffb04 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used addr 23* addr 22* addr 21* addr 20* addr 19 addr 18 addr 17 addr 16 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rambal ?array base address register low $yffb06 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 addr 15 addr 14 addr 13 addr 12 addr 11 addr 10 addr 9 addr 8 addr 7 addr 6 addr 5 addr 4 addr 3 addr 2 addr 1 addr 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 101 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 102 MC68HC16Z1ts/d 7 general-purpose timer module the gpt is a simple, yet flexible 11-channel timer used in systems where a moderate degree of external visibility and control is required. the gpt consists of two nearly independent submodules, the compare/ capture unit, and the pulse-width modulator. refer to the following block diagram of the gpt. figure 17 gpt block diagram gpt input capture/output compare pins are bidirectional and can be used to form an 8-bit parallel port. the pulse-width modulator outputs can be used as general-purpose outputs. the pai and pclk inputs can be used as general-purpose inputs. pulse accumulator pwm unit bus interface imb capture/compare unit prescaler pgp0/ic1 pgp1/ic2 pgp2/ic3 pclk pwmb pwma pai pgp7/ic4/oc5/oc1 pgp6/oc4/oc1 pgp5/oc3/oc1 pgp4/oc2/oc1 pgp3/oc1 gpt block .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 103 y = m111, where m is the logic state of the modmap (mm) bit in the simcr 7.1 capture/compare unit the capture/compare unit features three input capture channels, four output compare channels, and one input capture/output compare channel (function selected by control register). these channels share a 16-bit free-running counter (tcnt), which derives its clock from seven stages of a 9-stage prescaler or from external clock input pclk. this section also contains one pulse accumulator channel. the pulse accumulator logic includes its own 8-bit counter and can operate in either event counting mode or gated time accumulation mode. the following block diagrams show gpt compare/capture functions and the prescaler. table 20 gpt address map address 15 8 7 0 $yff900 gpt module configuration (gptmcr) $yff902 (reserved for test) $yff904 interrupt configuration (icr) $yff906 pgp data direction (ddrgp) pgp data (portgp) $yff908 oc1 action mask (oc1m) oc1 action data (oc1d) $yff90a timer counter (tcnt) $yff90c pa control (pactl) pa counter (pacnt) $yff90e input capture 1 (tic1) $yff910 input capture 2 (tic2) $yff912 input capture 3 (tic3) $yff914 output compare 1 (toc1) $yff916 output compare 2 (toc2) $yff918 output compare 3 (toc3) $yff91a output compare 4 (toc4) $yff91c input capture 4/output compare 5 (ti4/o5) $yff91e timer control 1 (tctl1) timer control 2 (tctl2) $yff920 timer mask 1 (tmsk1) timer mask 2 (tmsk2) $yff922 timer flag 1 (tflg1) timer flag 2 (tflg2) $yff924 force compare (cforc) pwm control c (pwmc) $yff926 pwm control a (pwma) pwm control b (pwmb) $yff928 pwm count (pwmcnt) $yff92a pwma buffer (pwmbufa) pwmb buffer (pwmbufb) $yff92c gpt prescaler (prescl) $yff92e? $yff93f reserved .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 104 MC68HC16Z1ts/d figure 18 gpt compare/capture block diagram pgp7/ ic4/ oc5/ oc1 pgp6/ oc4/ oc1 16-bit latch clk tic1 (hi) 16-bit comparator = ic3f oc2f oc3f i4/o5f tflg1 tmsk1 ic1f ic1i 1 ic2f ic2i 2 ic3i 3 oc4f i4/o5i 16-bit timer bus 16-bit free-running counter tcnt (hi) tof toi 9 1 of 8 select cpr2 cpr1 cpr0 prescaler?ivide by 4, 8, 16, 32, 64, 128, or 256 system clock i4/o5 oc1i 4 foc1 oc2i 5 foc2 oc3i 6 foc3 oc4i 7 foc4 8 foc5 status flags force output compare interrupt enables parallel port pin control oc5 ic4 cforc 16-bit timer bus oc1f bit-0 bit-1 bit-2 bit-3 bit-4 bit-5 bit-6 bit-7 pin functions pgp0/ ic1 pgp4/ oc2/ oc1 pgp5/ oc3/ oc1 pclk interrupt requests 16 cc block tcnt (lo) pgp1/ ic2 pgp2/ ic3 pgp3/ oc1 tic1 (lo) 16-bit latch clk tic2 (hi) tic2 (lo) 16-bit latch clk tic3 (hi) tic3 (lo) toc1 (hi) toc1 (lo) toc2 (hi) toc2 (lo) toc3 (hi) toc3 (lo) toc4 (hi) toc4 (lo) 16-bit latch clk ti4/o5 (hi) ti4/o5 (lo) 16-bit comparator = 16-bit comparator = 16-bit comparator = 16-bit comparator = .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 105 figure 19 prescaler block diagram 7.2 pulse-width modulator the pulse-width modulation submodule has two output pins. the outputs are periodic waveforms con- trolled by a single frequency whose duty cycles can be independently selected and modified by user software. each pwm can be independently programmed to run in fast or slow mode. the pwm unit has its own 16-bit free-running counter, which is clocked by an output of the nine-stage prescaler (the same prescaler used by the compare/capture unit) or by the clock input pin, pclk. to pulse accumulator cpr2 cpr1 cpr0 ppr2 ppr1 ppr0 to pulse accumulator to pulse accumulator to pwm unit to capture/ compare timer select select synchronizer and digital filter pclk pin divider ? 256 ? 128 ? 64 ? 32 ? 16 ? 8 ? 4 ext ? 128 ? 64 ? 32 ? 16 ? 8 ? 4 ? 2 ext system clock ? 512 ext ? 256 ? 128 ? 64 ? 32 ? 16 ? 8 ? 4 ? 512 ? 2 gpt prescaler block .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 106 MC68HC16Z1ts/d figure 20 pwm unit block diagram 7.3 gpt registers the gptmcr contains parameters for configuring the gpt. gptmcr ?gpt module configuration register $yff900 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stop frz1 frz0 stopp incp 0 0 0 supv 0 0 0 iarb3 iarb2 iarb1 iarb0 reset: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 zero detector 16-bit counter pwma register pwmb register pwmbufa register pwmbufb register comparator a comparator b multiplexer a multiplexer b sfb bit sfa bit f1a bit f1b bit latch r s latch r s zero detector pwmb pin pwma pin from prescaler clock 16-bit timer bus 16-bit data bus 8-bit 8-bit 16 pwm block 16-bit 16-bit 16-bit 0?4 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 107 stop ?stop clocks 0 = internal clocks not shut down 1 = internal clocks shut down frz1 ?not implemented at this time frz0 ?freeze response 0 = ignore freeze 1 = freeze the current state of the gpt stopp ?stop prescaler 0 = normal operation 1 = stop prescaler and pulse accumulator from incrementing. ignore changes to input pins. incp ?increment prescaler 0 = has no meaning 1 = if stopp is asserted, increment prescaler once and clock input synchronizers once. supv ?supervisor/unrestricted data space 0 = registers with access controlled by supv are unrestricted (fc2 is a don't care). 1 = registers with access controlled by supv are restricted when fc2 = 1. because the cpu16 in the MC68HC16Z1 operates in supervisor mode only (fc2 is always logic level one), this bit has no effect. iarb[3:0] ?interrupt arbitration identification to enable interrupt arbitration, system software must set this field to a value between $f?1; $f is the highest priority. this field is initialized to $0 during reset. if the cpu recognizes a gpt interrupt request while iarb = $0, a spurious interrupt exception is taken. mtr ?gpt module test register (reserved) $yff902 this address is currently unused and returns zeros if read. it is reserved for gpt factory test. ipa ?interrupt priority adjust specifies which gpt interrupt source is given highest internal priority ipl ?interrupt priority level specifies the priority level of interrupts generated by the gpt. ivba ?interrupt vector base address most significant nibble of interrupt vector numbers generated by the gpt. when gpt pins are used as an 8-bit port, ddrgp determines whether pins are input or output and portgp holds the 8-bit data. ddrgp[7:0] ?port gp data direction register 0 = input only 1 = output when portgp is used for general-purpose i/o, each bit in the ddrgp determines whether the cor- responding portgp bit is input or output. icr ?gpt interrupt configuration register $yff904 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ipa 0 ipl ivba 0 0 0 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ddrgp/portgp ?port gp data direction register/port gp data register $yff906 15 8 7 0 ddrgp portgp reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 108 MC68HC16Z1ts/d all oc outputs can be controlled by the action of oc1. oc1m contains a mask that determines which pins are affected. oc1d determines what the outputs are. oc1m[5:1] ?oc1 mask field 0 = corresponding output compare pin is not affected by oc1 compare. 1 = corresponding output compare pin is affected by oc1 compare. oc1m[5:1] correspond to oc[5:1]. oc1d[5:1] ?oc1 data field 0 = if oc1 mask bit is set, clear the corresponding output compare pin on oc1 match. 1 = if oc1 mask bit is set, set the corresponding output compare pin on oc1 match. oc1d[5:1] correspond to oc[5:1]. tcnt ?timer counter register $yff90a tcnt is the 16-bit free-running counter associated with the input capture, output compare, and pulse accumulator functions of the gpt module. pactl enables the pulse accumulator and selects either event counting or gated mode. in event count- ing mode, pacnt is incremented each time an event occurs. in gated mode, it is incremented by an internal clock. pais ?pai pin state (read only) paen ?pulse accumulator system enable 0 = pulse accumulator disabled 1 = pulse accumulator enabled pamod ?pulse accumulator mode 0 = external event counting 1 = gated time accumulation pedge ?pulse accumulator edge control the effects of pedge and pamod are shown in the following table. pclks ?pclk pin state (read only) oc1m/oc1d ?oc1 action mask register/oc1 action data register $yff908 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0c1m 0 0 0 0c1d 0 0 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pactl/pacnt ?pulse accumulator control register/counter $yff90c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pais paen pamod pedge pclks i4/o5 paclk pulse accumulator counter reset: u 0 0 0 u 0 0 0 0 0 0 0 0 0 0 0 pamod pedge effect 0 0 pai falling edge increments counter 0 1 pai rising edge increments counter 1 0 zero on pai inhibits counting 1 1 one on pai inhibits counting .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 109 i4/o5 ?input capture 4/output compare 5 0 = output compare 5 enabled 1 = input capture 4 enabled paclk[1:0] ?pulse accumulator clock select (gated mode) pacnt ?pulse accumulator counter eight-bit read/write counter used for external event counting or gated time accumulation. tic[1:3] ?input capture registers 1? $yff90e, $yff910, $yff912 the input capture registers are 16-bit read-only registers which are used to latch the value of tcnt when a specified transition is detected on the corresponding input capture pin. they are reset to $ffff. toc[1:4] ?output compare registers 1? $yff914, $yff916, $yff918, $yff91a the output compare registers are 16-bit read/write registers which can be used as output waveform controls or as elapsed time indicators. for output compare functions, they are written to a desired match value and compared against tcnt to control specified pin actions. they are reset to $ffff. ti4/o5 ?input capture 4/output compare 5 register $yff91c this register serves either as input capture register 4 or output compare register 5, depending on the state of i4/o5 in pactl. tctl1 determines output compare mode and output logic level. tctl2 determines the type of input capture to be performed. om/ol[5:2] ?output compare mode bits and output compare level bits each pair of bits specifies an action to be taken when output comparison is successful. edge[4:1] ?input capture edge control bits each pair of bits configures input sensing logic for the corresponding input capture. paclk[1:0] pulse accumulator clock selected 00 system clock divided by 512 01 same clock used to increment tcnt 10 tof flag from tcnt 11 external clock, pclk tctl1/tctl2 ?timer control registers 1? $yff91e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 om5 ol5 om4 ol4 om3 ol3 om2 ol2 edge4 edge3 edge2 edge1 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 om/ol[5:2] action taken 00 timer disconnected from output logic 01 toggle ocx output line 10 clear ocx output line to 0 11 set ocx output line to 1 edge[4:1] configuration 00 capture disabled 01 capture on rising edge only 10 capture on falling edge only 11 capture on any (rising or falling) edge .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 110 MC68HC16Z1ts/d tmsk1 enables oc and ic interrupts. tmsk2 controls pulse accumulator interrupts and tcnt func- tions. i4/o5i ?input capture 4/output compare 5 interrupt enable 0 = ic4/oc5 interrupt disabled 1 = ic4/oc5 interrupt requested when i4/o5f flag in tflg1 is set oci[4:1] ?output compare interrupt enable 0 = oc interrupt disabled 1 = oc interrupt requested when oc flag set oci[4:1] correspond to oc[4:1]. ici[3:1] ?input capture interrupt enable 0 = ic interrupt disabled 1 = ic interrupt requested when ic flag set ici[3:1] correspond to ic[3:1]. toi ?timer overflow interrupt enable 0 = timer overflow interrupt disabled 1 = interrupt requested when tof flag is set paovi ?pulse accumulator overflow interrupt enable 0 = pulse accumulator overflow interrupt disabled 1 = interrupt requested when paovf flag is set paii ?pulse accumulator input interrupt enable 0 = pulse accumulator interrupt disabled 1 = interrupt requested when paif flag is set cprout ?compare/capture unit clock output enable 0 = normal operation for oc1 pin 1 = tcnt clock driven out oc1 pin cpr[2:0] ?timer prescaler/pclk select field this field selects one of seven prescaler taps or pclk to be tcnt input. tmsk1/tmsk2 ?timer interrupt mask registers 1? $yff920 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 i4/o5i oci ici toi 0 paovi paii cprout cpr reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cpr[2:0] system clock divide-by factor 000 4 001 8 010 16 011 32 100 64 101 128 110 256 111 pclk .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 111 these registers show condition flags that correspond to various gpt events. if the corresponding inter- rupt enable bit in tmsk1/tmsk2 is set, an interrupt occurs. i4/o5f ?input capture 4/output compare 5 flag when i4/o5 in pactl is 0, this flag is set each time tcnt matches the value in toc5. when i4/o5 in pactl is 1, the flag is set each time a selected edge is detected at the i4/o5 pin. ocf[4:1] ?output compare flags an output compare flag is set each time tcnt matches the corresponding toc register. ocf[4:1] cor- respond to oc[4:1]. icf[3:1] ?input capture flags a flag is set each time a selected edge is detected at the corresponding input capture pin. icf[3:1] cor- respond to ic[3:1]. tof ?timer overflow flag this flag is set each time tcnt advances from a value of $ffff to $0000. paovf ?pulse accumulator overflow flag this flag is set each time the pulse accumulator counter advances from a value of $ff to $00. paif ?pulse accumulator flag in event counting mode, this flag is set when an active edge is detected on the pai pin. in gated time accumulation mode, paif is set at the end of the timed period. setting a bit in cforc causes a specific output on oc or pwm pins. pwmc sets pwm operating con- ditions. foc[5:1] ?force output compare 0 = has no meaning 1 = causes pin action programmed for corresponding oc pin, but the oc flag is not set. foc[5:1] correspond to oc[5:1]. fpwma ?force pwma value 0 = normal pwma operation 1 = the value of f1a is driven out on the pwma pin, regardless of the state of pprout. fpwmb ?force pwmb value 0 = normal pwmb operation 1 = the value of f1b is driven out on the pwmb pin. pprout ?pwm clock output enable 0 = normal pwm operation on pmwa 1 = tcnt clock driven out pwma pin tflg1/tflg2 ?timer interrupt flag registers 1? $yff922 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i4/o5f ocf icf tof 0 paovf paif 0 0 0 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cforc/pwmc ?compare force register/pwm control register $yff924 15 11 10 9 8 7 6 4 3 2 1 0 foc 0 fpwma fpwmb pprout ppr sfa sfb f1a f1b reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 112 MC68HC16Z1ts/d ppr[2:0] ?pwm prescaler/pclk select this field selects one of seven prescaler taps or pclk to be pwmcnt input. sfa ?pwma slow/fast select 0 = pwma period is 256 pwmcnt increments long. 1 = pwma period is 32768 pwmcnt increments long. sfb ?pwmb slow/fast select 0 = pwmb period is 256 pwmcnt increments long. 1 = pwmb period is 32768 pwmcnt increments long. the following table shows the effects of sf settings on pwm frequency (16.78-mhz system clock). f1a ?force logic level one on pwma 0 = force logic level zero output on pwma pin 1 = force logic level one output on pwma pin f1b ?force logic level one on pwmb 0 = force logic level zero output on pwmb pin 1 = force logic level one output on pwmb pin pwma/pwmb ?pwm registers a/b $yff926, $yff927 these registers are associated with the pulse-width value of the pwm output on the corresponding pwm pin. a value of $00 loaded into one of these registers results in a continuously low output on the corresponding pin. a value of $80 results in a 50% duty cycle output. maximum value ($ff) selects an output that is high for 255/256 of the period. pwmcnt ?pwm count register $yff928 pwmcnt is the 16-bit free-running counter associated with the pwm functions of the gpt module. pwmbufa/b ?pwm buffer registers a/b $yff92a, $yff92b these read-only registers contain values associated with the duty cycles of the corresponding pwm. reset state is $0000. prescl ?gpt prescaler $yff92c the 9-bit prescaler value can be read from bits [8:0] at this address. bits [15:9] always read as zeros. reset state is $0000. ppr[2:0] system clock divide-by factor 000 2 001 4 010 8 011 16 100 32 101 64 110 128 111 pclk ppr[2:0] prescaler tap sfa/b = 0 sfa/b = 1 000 div 2 = 8.39 mhz 32.8 khz 256 hz 001 div 4 = 4.19 mhz 16.4 khz 128 hz 010 div 8 = 2.10 mhz 8.19 khz 64.0 hz 011 div 16 = 1.05 mhz 4.09 khz 32.0 hz 100 div 32 = 524 khz 2.05 khz 16.0 hz 101 div 64 = 262 khz 1.02 khz 8.0 hz 110 div 128 = 131 khz 512 hz 4.0 hz 111 pclk pclk/256 pclk/32768 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 113 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 114 MC68HC16Z1ts/d 8 electrical characteristics this section contains electrical specification tables and reference timing diagrams. the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d q ja ) (1) where t a = ambient temperature, c q ja = package thermal resistance, junction-to-ambient, c/w p d = p int +p i/o p int = i dd v dd , watts ?chip internal power p i/o = power dissipation on input and output pins ?user determined for most applications p i/o < p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k ? (t j + 273 c) (2) solving equations 1 and 2 for k gives: k = p d + (t a + 273 c) + q ja p d 2 (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . 1. permanent damage can occur if maximum ratings are exceeded. exposure to voltages or currents in excess of recommended values affects device reliability. device modules may not operate normally while being exposed to electrical extremes. 2. although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields, take normal precautions to avoid exposure to voltages higher than maximum-rated voltages 3. ll pins except tstme /tsc. 4. all functional non-supply pins are internally clamped to v ss . all functional pins except extal, tstme /tsc, and xfc are internally clamped to v dd . 5. this parameter is periodically sampled rather than 100% tested. 6. power supply must maintain regulation within operating v dd range during instantaneous and operating maxi- mum current condition. 7. total input current for all digital input-only and all digital input/output pins must not exceed 10 ma. exceeding this limit can cause disruption of normal operation. table 21 maximum ratings rating symbol value unit supply voltage 1,2,5 v dd ?.3 to + 6.5 v input voltage 1,2,3,4,5 v in ?.3 to +6.5 v instantaneous maximum current single pin limit (applies to all pins) 1,4,5,6 i d 25 ma operating maximum current digital input disruptive current 4,5,6,7 v ss ?0.3 v in v dd + 0.3 i id ?00 to 500 ma operating temperature range MC68HC16Z1 ??suffix MC68HC16Z1 ??suffix MC68HC16Z1 ??suffix t a tl to th ?0 to 85 ?0 to 105 ?0 to 125 c storage temperature range t stg ?5 to 150 c table 22 thermal characteristics characteristic symbol value unit thermal resistance plastic 132-pin surface mount plastic 144-pin surface mount q ja 38 c/w .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 115 1. all internal registers retain data at 0 hz. 2. assumes that stable v ddsyn is applied, that an external filter capacitor with a value of 0.1 m f is attached to the xfc pin, and that the crystal oscillator is stable. lock time is measured from power-up to reset release. this specification also applies to the period required for pll lock after changing the w and y frequency control bits in the synthesizer control register (syncr) while the pll is running, and to the period required for the clock to lock after lpstop. 3. determined by the initial control voltage applied to the on-chip vco. the x bit in syncr controls a divide by two scaler on the system clock output. 4. short-term clkout stability is the average deviation from programmed frequency measured over a 2 m s interval at maximum f sys . long-term clkout stability is the average deviation from programmed frequency measured over a 1 ms interval at maximum f sys . stability is measured with a stable external clock applied ?variation in crystal oscillator frequency is additive to this figure. 5. this parameter is periodically sampled rather than 100% tested. table 23 clock control timing (v dd and v ddsyn = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , 32.768 khz reference) characteristic symbol min max unit pll reference frequency range f ref 25 50 khz system frequency 1 dc 16.78 on-chip pll frequency f sys 0.131 16.78 mhz external clock operation dc 16 pll lock time 2 t lpll ?0ms limp mode clock frequency 3 syncr x bit = 0 syncr x bit = 1 f limp f sys max/2 f sys max mhz clkout stability 4,5 short term long term c stab ?.0 ?.5 1.0 0.5 % .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 116 MC68HC16Z1ts/d table 24 dc characteristics (v dd and v ddsyn = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic symbol min max unit input high voltage v ih 0.7 (v dd )v dd + 0.3 v input low voltage v il v ss ?0.3 0.2 (v dd )v input hysteresis 1,9 v hys 0.5 v input leakage current 2 v in =v dd or v ss all input-only pins except adc pins i in ?.5 2.5 m a high impedance (off-state) leakage current 2 v in =v dd or v ss all input/output and output pins i oz ?.5 2.5 m a cmos output high voltage 2,3 i oh = ?0.0 m a group 1, 2, 4 input/output and all output pins v oh v dd ?0.2 v cmos output low voltage 2 i ol = 10.0 m a group 1, 2, 4 input/output and all output pins v ol 0.2 v output high voltage 2,3 i oh =?.8 ma group 1, 2, 4 input/output and all output pins v oh v dd ?0.8 v output low voltage 2 i ol = 1.6 ma group 1 i/o pins, clkout, freeze/quot, ipipe0 i ol = 5.3 ma group 2 and group 4 i/o pins, csboot , bg /cs i ol = 12 ma group 3 v ol 0.4 0.4 0.4 v three state control input high voltage v ihtsc 1.6 (v dd ) 9.1 v data bus mode select pull-up current 5 v in = v il data[15:0] v in = v ih data[15:0] i msp ?5 ?20 m a v dd supply current 6 run 4 lpstop, 32.768 khz crystal, vco off (stsim = 0) lpstop (external clock input frequency = maximum f sys ) i dd s idd s idd 110 350 5 ma m a ma clock synthesizer operating voltage v ddsyn 4.5 5.5 v v ddsyn supply current 6 32.768 khz crystal, vco on, maximum f sys external clock, maximum f sys lpstop, 32.768 khz crystal, vco off (stsim = 0) 32.768 khz crystal, v dd powered down i ddsyn i ddsyn s iddsyn i ddsyn 1 5 150 100 ma ma m a m a ram standby voltage 7 specified v dd applied v dd = v ss v sb 0.0 3.0 5.5 5.5 v ram standby current 7 specified v dd applied v dd = v ss i sb i sb ?.5 2.5 50 m a m a power dissipation 8 p d 605 mw input capacitance 2,9 all input-only pins except adc pins all input/output pins c in 10 20 pf load capacitance 2 group 1 i/o pins and clkout, freeze/quot, ipipe0 group 2 i/o pins and csboot , bg /cs group 3 i/o pins group 4 i/o pins c l 90 100 130 200 pf .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 117 notes: 1. applies to: port ada [7:0] ?an[7:0] port e [7:4] siz[1:0], as , ds port f [7:0] irq[7:1] , modclk port gp [7:0] ?ic4/oc5/oc1, ic[3:1], oc[4:1]/oc1 port qs [7:0] ?txd, pcs[3:1],?cs0/ss , sck, mosi, miso bkpt /dsclk, dsi/ipipe1, pai, pclk, reset , rxd, tstme /tsc 2. input-only pins: tstme /tsc, bkpt /dsclk, pai, pclk, rxd output-only pins: csboot , bg /cs1 , clkout, freeze/quot, ds0/ipipe0, pwma, pwmb input/output pins: group 1: port gp [7:0] ?ic4/oc5/oc1, ic[3:1], oc[4:1]/oc1 data[15:0], dsi/ipipe1 group 2: port c [6:0] ?addr[22:19]/cs[9:6] , fc[2:0]/cs[5:3] port e [7:0] ?iz[1:0], as , ds , avec , dsack[1:0] port f [7:0] ?irq[7:1] , modclk port qs [7:3] ?txd, pcs[3:1],?cs0/ss addr23/cs10 /eclk, addr[18:0], r/w , berr , br /cs0 , bgack /cs2 group 3: halt , reset group 4: miso, mosi, sck 3. does not apply to halt and reset because they are open drain pins. does not apply to port qs [7:0] (txd, pcs[3:1],?cs0/ss , sck, mosi, miso) in wired-or mode. 4. current measured with system clock frequency of 16.78 mhz, all modules active. 5. use of an active pulldown device is recommended. 6.total operating current is the sum of the appropriate v dd supply and v ddsyn supply currents. 7.the sram module will not switch into standby mode as long as v sb does not exceed v dd by more than 0.5 volt. the sram array cannot be accessed while the module is in standby mode. 8. power dissipation measured with system clock frequency of 16.78 mhz, all modules active. power dissipation is calculated using the following expression: p d = maximum v dd (i ddsyn + i dd ) 9. this parameter is periodically sampled rather than 100% tested. .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 118 MC68HC16Z1ts/d table 25 ac timing (v dd and v ddsyn = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol min max unit f1 2 frequency of operation (32.768 khz crystal) f 0.13 16.78 mhz 1 clock period t cyc 59.6 ns 1a eclk period t ecyc 476 ns 1b 3 external clock input period t xcyc 64 ns 2, 3 clock pulse width t cw 24 ns 2a, 3a eclk pulse width t ecw 236 ns 2b, 3b 3 external clock input high/low time t xchl 32 ns 4, 5 clkout rise and fall time t crf ?ns 4a, 5a rise and fall time (all outputs except clkout) t rf ?ns 4b, 5b external clock input rise and fall time t xcrf ?ns 6 clock high to addr, fc, size valid t chav 029ns 7 clock high to addr, data, fc, size high impedance t chazx 059ns 8 clock high to addr, fc, size, invalid t chazn 0ns 9 clock low to as , ds , cs asserted t clsa 225ns 9a 4 as to ds or cs asserted (read) t stsa ?5 15 ns 11 addr, fc, size valid to as , cs , (and ds read) asserted t avsa 15 ns 12 clock low to as , ds , cs negated t clsn 229ns 13 as , ds , cs negated to addr, fc, size invalid (address hold) t snai 15 ns 14 as , cs width asserted t swa 100 ns 14a ds , cs width asserted (write) t swaw 45 ns 14b as , cs width asserted (fast cycle) t swdw 40 ns 15 5 as , ds , cs width negated t sn 40 ns 16 clock high to as , ds , r/w high impedance t chsz ?9ns 17 as , ds , cs negated to r/w high t snrn 15 ns 18 clock high to r/w high t chrh 029ns 20 clock high to r/w low t chrl 029ns 21 r/w high to as , cs asserted t raaa 15 ns 22 r/w low to ds , cs asserted (write) t rasa 70 ns 23 clock high to data out valid t chdo ?9ns 24 data out valid to negating edge of as , cs t dvasn 15 ns 25 ds , cs negated to data out invalid (data out hold) t sndoi 15 ns 26 data out valid to ds , cs asserted (write) t dvsa 15 ns 27 data in valid to clock low (data setup) t dicl 5ns 27a late berr , halt asserted to clock low (setup time) t belcl 20 ns 28 as , ds negated to dsackx , berr , halt , avec negated t sndn 080ns 29 6 ds , cs negated to data in invalid (data in hold) t sndi 0ns 29a 6, 7 ds , cs negated to data in high impedance t shdi ?5ns 30 6 clkout low to data in invalid (fast cycle hold) t cldi 15 ns 30a 6 clkout low to data in high impedance t cldh ?0ns 31 8 dsackx asserted to data in valid t dadi ?0ns 33 clock low to bg asserted/negated t clban ?9ns .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 119 35 9 br asserted to bg asserted t braga 1t cyc 37 bgack asserted to bg negated t gagn 12t cyc 39 bg width negated t gh 2t cyc 39a bg width asserted t ga 1t cyc 46 r/w width asserted (write or read) t rwa 150 ns 46a r/w width asserted (fast write or read cycle) t rwas 90 ns 47a asynchronous input setup time br , bgack , dsackx , berr , avec , halt t aist 5ns 47b asynchronous input hold time t aiht 15 ns 48 10 dsackx asserted to berr , halt asserted t daba ?0ns 53 data out hold from clock high t doch 0ns 54 clock high to data out high impedance t chdh ?8ns 55 r/w asserted to data bus impedance change t radc 40 ns 70 clock low to data bus driven (show cycle) t scldd 029ns 71 data setup time to clock low (show cycle) t sclds 15 ns 72 data hold from clock low (show cycle) t scldh 10 ns 73 bkpt input setup time t bkst 15 ns 74 bkpt input hold time t bkht 10 ns 75 mode select setup time t mss 20 t cyc 76 mode select hold time t msh 0ns 77 reset assertion time 11 t rsta 4t cyc 78 reset rise time 12 t rstr ?0t cyc 100 clkout high to phase 1 asserted 13 t chp1a 3 40 ns 101 clkout high to phase 2 asserted 13 t chp2a 3 40 ns 102 phase 1 valid to as or ds asserted 13 t p1vsa ?0ns 103 phase 2 valid to as or ds negated 13 t p2vsn ?0ns 104 as or ds valid to phase 1 asserted 13 t sap1a ?0ns 105 as or ds negated to phase 2 negated 13 t snp2n ?0ns table 25 ac timing (continued) (v dd and v ddsyn = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol min max unit .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 120 MC68HC16Z1ts/d notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. 2. minimum system clock frequency is four times the crystal frequency, subject to specified limits. 3. minimum external clock high and low times are based on a 50% duty cycle. the minimum allowable t xcyc period will be reduced when the duty cycle of the external clock signal varies. the relationship between external clock input duty cycle and minimum t xcyc is expressed: minimum t xcyc period = minimum t xchl / (50% ?external clock input duty cycle tolerance). to achieve maximum operating frequency (f sys ) while using an external clock input, adjust clock input duty cycle to obtain a 50% duty cycle on clkout. 4. specification 9a is the worst-case skew between as and ds or cs . the amount of skew depends on the relative loading of these signals. when loads are kept within specified limits, skew will not cause as and ds to fall out- side the limits shown in specification 9. 5. if multiple chip selects are used, cs width negated (specification 15) applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select. the cs width negated specification between multiple chip selects does not apply to chip selects being used for synchronous eclk cycles. 6. hold times are specified with respect to ds or cs on asynchronous reads and with respect to clkout on fast cycle reads. the user is free to use either hold time. 7. maximum value is equal to (t cyc / 2) + 25 ns. 8. if the asynchronous setup time (specification 47a) requirements are satisfied, the dsackx low to data setup time (specification 31) and dsackx low to berr low setup time (specification 48) can be ignored. the data must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. berr must satisfy only the late berr low to clock low setup time (specification 27a) for the following clock cycle. 9. to ensure coherency during every operand transfer, bg is not asserted in response to br until after all cycles of the current operand transfer are complete. 10. in the absence of dsackx , berr is an asynchronous input using the asynchronous setup time (specification 47a). 11. after external reset negation is detected, a short transition period (approximately 2 t cyc ) elapses, then the sim drives reset low for 512 t cyc . 12. external logic must pull reset high during this period in order for normal mcu operation to begin. 13. eight pipeline states are multiplexed into ipipe[1:0]. the multiplexed signals have two phases. 14. address access time = (2.5 + ws) t cyc ?t chav ?t dicl chip select access time = (2 + ws) t cyc ?t clsa ?t dicl where: ws = number of wait states. when fast termination is used (2 clock bus) ws = ?. .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 121 notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. 2. when previous bus cycle is not an eclk cycle, the address may be valid before eclk goes low. 3. address access time = t ecyc ?t ead ?t edsr 4. chip select access time = t ecyc ?t ecsd ?t edsr table 26 background debugging mode timing (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol min max unit b0 dsi input setup time t dsisu 15 ns b1 dsi input hold time t dsih 10 ns b2 dsclk setup time t dscsu 15 ns b3 dsclk hold time t dsch 10 ns b4 dso delay time t dsod ?5ns b5 dsclk cycle time t dsccyc 2 t cyc b6 clkout high to freeze asserted/negated t frzan ?0ns b7 clkout high to ipipe1 high impedance t ifz ?0ns b8 clkout high to ipipe1 valid t if ?0ns b9 dsclk low time t dsclo 1t cyc table 27 eclk bus timing (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol min max unit e1 2 eclk low to address valid t ead ?0ns e2 eclk low to address hold t eah 10 ns e3 eclk low to cs valid (cs delay) t ecsd 150 ns e4 eclk low to cs hold t ecsh 15 ns e5 cs negated width t ecsn 30 ns e6 read data setup time t edsr 30 ns e7 read data hold time t edhr 15 ns e8 eclk low to data high impedance t edhz ?0ns e9 cs negated to data hold (read) t ecdh 0ns e10 cs negated to data high impedance t ecdz ?t cyc e11 eclk low to data valid (write) t eddw ?t cyc e12 eclk low to data hold (write) t edhw 5ns e13 cs negated to data hold (write) t echw 0ns e14 3 address access time (read) t eacc 386 ns e15 4 chip select access time (read) t eacs 296 ns e16 address setup time t eas 1/2 t cyc .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 122 MC68HC16Z1ts/d notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. 2. in formula, n = external sck rise + external sck fall time. table 28 qspi timing (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , 200 pf load on all qspi pins) num function symbol min max unit operating frequency master slave f op dc dc 1/4 1/4 system clock frequency system clock frequency 1 cycle time master slave t qcyc 4 4 510 t cyc t cyc 2 enable lead time master slave t lead 2 2 128 t cyc t cyc 3 enable lag time master slave t lag 2 1/2 sck t cyc 4 clock (sck) high or low time master slave 2 t sw 2 t cyc ? 60 2 t cyc ?n 255 t cyc ns ns 5 sequential transfer delay master slave (does not require deselect) t td 17 13 8192 t cyc t cyc 6 data setup time (inputs) master slave t su 30 20 ns ns 7 data hold time (inputs) master slave t hi 0 20 ns ns 8 slave access time t a ? t cyc 9 slave miso disable time t dis ? t cyc 10 data valid (after sck edge) master slave t v 50 50 ns ns 11 data hold time (outputs) master slave t ho 0 0 ns ns 12 rise time input output t ri t ro 2 30 ms ns 13 fall time input output t fi t fo 2 30 ms ns .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 123 1. below disruptive current conditions, the channel being stressed will have conversion values of $3ff for analog inputs greater than v rh and $000 for values less than v rl . this assumes that v rh v dda and v rl 3 v ssa due to the presence of the sample amplifier. other channels are not affected by non-disruptive conditions. 2. input signals with large slew rates or high frequency noise components cannot be converted accurately. these signals also interfere with conversion of other channels. 3. this parameter is periodically sampled rather than 100% tested. 4. applies to single pin only. 5. exceeding limit may cause conversion error on stressed channels and on unstressed channels. transitions within the limit do not affect device reliability or cause permanent damage. table 29 adc maximum ratings num parameter symbol min max unit 1 analog supply v dda ?0.3 6.5 v 2 internal digital supply v ddi ?0.3 6.5 v 3 reference supply v rh , v rl ?0.3 6.5 v 4v ss differential voltage v ssi ? v ssa ?0.1 0.1 v 5v dd differential voltage v ddi ? v dda ?6.5 6.5 v 6v ref differential voltage v rh ? v rl ?6.5 6.5 v 7v ref to v dda differential voltage v rh ? v dda ?6.5 6.5 v 8 disruptive input current 1, 2, 3, 4 v ssa ?0.3 v ina v dda + 2 i na ?15 15 m a 9 maximum input current 5, 3 v ssa ?1 v ina v dda + 3.5 i ma ?500 500 m a .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 124 MC68HC16Z1ts/d 1. refers to operation over full temperature and frequency range. 2. to obtain full-scale, full-range results, v ssa v rl v indc v rh v dda. 3. accuracy tested and guaranteed at v rh ? v rl 5.0 v 10%. 4. current measured at maximum system clock frequency with adc active. 5. maximum leakage occurs at maximum operating temperature. current decreases by approximately one- half for each 10 c decrease from maximum temperature. 1. assumes 2.1 mhz adc clock and selection of minimum sample time (2 adc clocks). table 30 adc dc electrical characteristics (operating) (v ss = 0 vdc, adclk = 2.1 mhz, t a within operating temperature range) num parameter symbol min max unit 1 analog supply 1 v dda 4.5 5.5 v 2 internal digital supply 1 v ddi 4.5 5.5 v 3v ss differential voltage v ssi ? v ssa ?1.0 1.0 mv 4v dd differential voltage v ddi ? v dda ?1.0 1.0 v 5 reference voltage low 2,3 v rl v ssa v dda / 2 v 6 reference voltage high 2,3 v rh v dda / 2 v dda v 7 v ref differential voltage 3 v rh ? v rl 4.5 5.5 v 8 input voltage 2 v indc v ssa v dda v 9 input high, port ada v ih 0.7 (v dda )v dda + 0.3 v 10 input low, port ada v il v ssa ?0.3 0.2 (v dda )v 15 analog supply current 4 i dda 1.0 ma 16 analog supply current, lpstop s dda tbd m a 17 reference supply current i ref 250 m a 18 input current, off channel 5 i off 250 na 19 total input capacitance, not sampling c inn ?0pf 20 total input capacitance, sampling c ins ?5pf table 31 adc ac characteristics (operating) (v dd and v dda = 5.0 vdc 10%, v ss = 0 vdc, t a within operating temperature range) num parameter symbol min max unit 1 imb clock frequency f iclk 2.0 16.78 mhz 2 adc clock frequency f adclk 0.5 2.1 mhz 3 8-bit conversion time (16 adc clocks) 1 t conv 7.62 m s 4 10-bit conversion time (18 adc clocks) 1 t conv 8.58 m s 5 stop recovery time t sr ?0 m s .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 125 1. v rh ?v rl 3 5.12 v; v dda ?v ssa = 5.12 v 2. at v ref = 5.12 v, one 10-bit count = 5 mv and one 8-bit count = 20 mv. 3. 8-bit absolute error of 1 count (20 mv) includes 1/2 count (10 mv) inherent quantization error and 1/2 count (10 mv) circuit (differential, integral, and offset) error. 4. 10-bit absolute error of 2.5 counts (12.5 mv) includes 1/2 count (2.5 mv) inherent quantization error and 2 counts (10 mv) circuit (differential, integral, and offset) error. 5. maximum source impedance is application-dependent. error resulting from pin leakage depends on junction leakage into the pin and on leakage due to charge-sharing with internal capacitance. in the following expres- sions, expected error in result value due to leakage is expressed in voltage (v errx ). error from junction leakage is a function of external source impedance and input leakage current: v errj = r s i off where i off is a function of operating temperature. (see table a?0, note 4). charge-sharing leakage is a function of adc clock speed, number of channels scanned, and source imped- ance: for 10-bit conversion, v err10 =.25 pf v dda r s adclk ? (9 number of channels) for 8-bit conversion, v err8 =.25 pf v dda r s adclk ? (8 number of channels) table 32 adc conversion characteristics (operating) (v dd and v dda = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , adclk = 2.1 mhz) num parameter symbol min typ max unit 1 8-bit resolution 1 1 count 20 mv 2 8-bit differential nonlinearity 2 dnl ?5 .5 counts 3 8-bit integral nonlinearity 2 inl ? 1 counts 4 8-bit absolute error 2,3 ae ? 1 counts 5 10-bit resolution 1 1 count 5 mv 6 10-bit differential nonlinearity 2 dnl ? 1 counts 7 10-bit integral nonlinearity 2 inl ? 2 counts 8 10-bit absolute error 2,4 ae ?.5 2.5 counts 9 source impedance at input 5 r s 20 see note 5 k .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 126 MC68HC16Z1ts/d timing diagrams note: timing shown with respect to 20% and 70% v dd . figure 21 clkout output timing diagram note: timing shown with respect to 20% and 70% v dd . pulse width shown with respect to 50% v dd . figure 22 external clock input timing diagram note: timing shown with respect to 20% and 70% v dd . figure 23 eclk output timing diagram 16 clkout tim clkout 4 5 2 1 3 16 ext clk input tim extal 4b 5b 2b 1b 3b 16 eclk output tim eclk 4a 5a 2a 1a 3a .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 127 figure 24 read cycle timing diagram 16 rd cyc tim clkout s0 s1 s2 s3 s4 s5 27 9a 11 13 8 6 a20?23 fc0?c2 siz0, siz1 ds cs r/w as dsack0 dsack1 d0?15 berr 20 18 47b 47a asynchronous inputs halt bkpt 9 15 14 12 46 47a 28 21 29 31 48 73 74 27a 29a ipipe0 ipipe1 phase 1 phase 2 100 104 103 105 101 102 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 128 MC68HC16Z1ts/d figure 25 write cycle timing diagram 16 wr cyc tim clkout s0 s1 s2 s3 s4 s5 54 11 13 8 6 addr[23:20] fc[2:0] siz0, siz1 ds cs r/w as dsack0 dsack1 data[15:0] berr 20 halt bkpt 9 15 14 12 46 17 47a 28 22 25 55 48 73 74 27a 53 26 14a 9 23 101 ipipe0 ipipe1 phase 1 phase 2 100 102 104 103 105 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 129 figure 26 show cycle timing diagram figure 27 data bus mode select timing diagram clkout s0 s41 s42 s0 s1 s2 addr[23:20] r/w as ds data[15:0] bkpt s43 16 shw cyc tim 6 8 12 9 18 20 72 71 70 15 show cycle start of external cycle 101 ipipe0 ipipe1 phase 2 100 102 104 103 105 phase 2 phase 1 27a phase 1 16 rst/mode sel tim reset data[15:0], 75 76 77 78 modclk, bkpt .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 130 MC68HC16Z1ts/d figure 28 bus arbitration timing diagram ?active bus case 16 bus arb tim clkout s0 s1 s2 s3 s4 addr[23:0] data[15:0] 7 s98 a5 a5 a2 47a 39a 35 33 33 16 s5 as ds r/w dsack0 dsack1 br bg bgack 37 phase 1 phase 2 100 102 104 103 105 101 ipipe0 ipipe1 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 131 figure 29 bus arbitration timing diagram ?idle bus case 16 bus arb tim idle clkout a0 a5 addr[23:0] data[15:0] a2 a3 a0 a5 br as bg bgack 47a 33 33 47a 37 47a 35 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 132 MC68HC16Z1ts/d figure 30 fast termination read cycle timing diagram clkout s0 s1 s4 s5 s0 18 9 6 addr[23:0] fc[2:0] siz[1:0] ds cs r/w as data[15:0] 8 bkpt 12 46a 30 29a 20 74 30a 29 phase 1 phase 2 100 102 104 103 105 101 ipipe0 ipipe1 27 73 14b .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 133 figure 31 fast termination write cycle timing diagram clkout s0 s1 s4 s5 s0 20 9 6 addr[23:0] fc[1:0] siz[1:0] ds cs r/w as data[15:0] 14b 8 bkpt 100 101 ipipe0 ipipe1 phase 1 12 46a 23 27a phase 2 24 18 25 105 102 104 103 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 134 MC68HC16Z1ts/d note: shown with eclk = system clock/8 ?ediv bit in clock synthesizer control register (syncr) = 0. figure 32 eclk timing diagram hc16 e cycle tim clkout addr[23:0] cs eclk data[15:0] e1 2a 3a e2 e5 e4 e3 e9 e7 e8 e10 e12 e14 e13 1a data[15:0] e15 e11 write read write e6 r/w .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 135 note: as and ds timing shown for reference only. figure 33 chip select timing diagram 16 chip sel tim 6 6 8 11 11 25 53 54 23 55 29a 29 27 46 46 14a 12 13 15 9 9 12 14 9 18 20 18 s0 s1 s2 s3 s4 s5 s0 s1 s2 s3 s4 s5 14 clkout addr[23:0] fc[2:0] siz[1:0] as ds cs r/w data[15:0] 21 17 17 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 136 MC68HC16Z1ts/d figure 34 background debugging mode timing diagram ?serial communication figure 35 background debugging mode timing diagram ?reeze assertion 16 bdm ser com tim b1 b3 b2 b0 b4 clkout freeze bkpt /dsclk ipipe1/dsi ipipe0/dso b5 b9 16 bdm frz tim b8 clkout freeze ipipe1/dsi b6 b7 b11 b6 b10 .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 137 figure 36 qspi timing master, cpha = 0 figure 37 qspi timing master, cpha = 1 16 qspi mast cpha0 13 11 6 10 12 4 4 13 12 3 2 5 1 data lsb in msb in msb out msb in msb out data lsb out port data 7 12 13 pcs[3:0] output pd miso input mosi output sck cpol=0 output sck cpol=1 output 16 qspi mast cpha1 13 11 10 12 4 4 13 12 3 2 5 1 msb pcs[3:0] output miso input msb msb out data lsb out port data 12 13 port data mosi output data lsb in msb in 7 6 1 sck cpol=0 output sck cpol=1 output .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 138 MC68HC16Z1ts/d figure 38 qspi timing slave, cpha = 0 figure 39 qspi timing slave, cpha = 1 13 10 13 7 6 8 11 9 11 12 4 13 12 3 2 5 1 data lsb out pd msb out msb in msb out msb in data lsb in ss input sck cpol=0 input sck cpol=1 input miso output mosi input 4 16 qspi slv cpha0 16 qspi slv cpha1 ss input 13 12 4 12 5 11 12 6 10 9 8 data slave lsb out pd msb out msb in data lsb in 7 4 1 2 10 pd 13 3 miso output sck cpol=1 input mosi input sck cpol=0 input .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 139 .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 140 MC68HC16Z1ts/d 9 summary of changes this is a partial revision. most of the publication remains the same, but the following changes were made to improve it. typographical errors that do not affect content are not annotated. page 2 ordering information. all currently available options added. page 5 block diagram revised. all pin functions shown, port mnemonics changed. page 6 pinout diagram revised. all pin functions shown, port mnemonics changed. page 7 144-pin diagram added. pages 8-9 corrected port assignments, new notes, changed b driver description. pages 10-12 corrected port assignments, new notes, changed b driver description. pages 13-16 revised register map, new pseudolinear maps. page 17 added xmsk, ymsk registers to diagram. page 41 sim memory map standardized. page 45 expanded iarb field description. pages 48-49 expanded system clock description. page 51 expanded and relocated pit description. page 65 new information concerning pe3. pages 66-69 new resets section. pages 70-72 new interrupts section. page 75 adc memory map standardized, result register mnemonics added. pages 76 &77 changed adc i/o port register mnemonics to reflect port name. page 77 changed prescaler rate selection values. page 83 qsm memory map standardized. pages 83 & 86 changed qsm i/o port register mnemonics to reflect port name. page 94 new qspi ram diagram. pages 90 & 91 changed spi br field mnemonic to spbr. page 97 changed sci br field mnemonic to scbr. page 102 sram memory map added. page 106 gpt memory map standardized. pages 106 & 110 changed gpt i/o port register mnemonics to reflect port name. pages 118-145 new electrical characteristics section. .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 141 notes .com .com .com .com 4 .com u datasheet
motorola MC68HC16Z1 142 MC68HC16Z1ts/d notes .com .com .com .com 4 .com u datasheet
MC68HC16Z1 motorola MC68HC16Z1ts/d 143 notes .com .com .com .com 4 .com u datasheet
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order this document by: m68hc16zec20/d ?motorola inc, 1995 semiconductor motorola technical data m68hc16 z series technical supplement 20.97 mhz electrical characteristics devices in the m68hc16 modular microcontroller family are built up from a selection of standard functional modules. microcontrollers in the m68hc16 z series contain the same central processing unit (cpu16) and system integration module (sim), and thus have similar electrical characteristics. m68hc16 devices that operate at clock frequencies of 20.97 mhz are now available. this publica- tion contains a new electrical characteristics appendix that supplements the MC68HC16Z1 user's manual (MC68HC16Z1um/ad) and the mc68hc16z2 user's manual (mc68hc16z2um/ad). the supplement contains the following updated specifications: table page maximum ratings ...................................................................................................... 2 typical ratings .......................................................................................................... 3 thermal characteristics ............................................................................................. 3 clock control timing ................................................................................................. 4 dc characteristics ..................................................................................................... 5 ac timing .................................................................................................................. 8 background debugging mode timing ..................................................................... 19 eclk bus timing .................................................................................................... 20 qspi timing ............................................................................................................ 21 adc maximum ratings ........................................................................................... 24 adc dc electrical characteristics (operating) ....................................................... 25 adc ac characteristics (operating) ....................................................................... 26 adc conversion characteristics (operating) .......................................................... 26 .com .com .com .com 4 .com u datasheet
motorola m68hc16zec20/d 2 notes: 1. permanent damage can occur if maximum ratings are exceeded. exposure to voltag- es or currents in excess of recommended values affects device reliability. device mod- ules may not operate normally while being exposed to electrical extremes. 2. although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields, take normal precautions to avoid exposure to voltag- es higher than maximum-rated voltages. 3. this parameter is periodically sampled rather than 100% tested. 4. all pins except tsc. 5. input must be current limited to the value specified. to determine the value of the re- quired current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 6. power supply must maintain regulation within operating v dd range during instanta- neous and operating maximum current. 7. all functional non-supply pins are internally clamped to v ss . all functional pins except extal and xfc are internally clamped to v dd . 8. total input current for all digital input-only and all digital input/output pins must not ex- ceed 10 ma. exceeding this limit can cause disruption of normal operation. table a? maximum ratings num rating symbol value unit 1 supply voltage 1,2,3 v dd ?0.3 to + 6.5 v 2 input voltage 1,2,3,4,5,7 vin ?0.3 to + 6.5 v 3 instantaneous maximum current single pin limit (all pins) 1,3,5,6 id 25 ma 4 operating maximum current digital input disruptive current 3,5,6,7,8 v negclmap @ ?0.3 v v posclamp @ v dd + 0.3 iid ?500 to 500 m a 5 operating temperature range c suffix ta tl to th ?40 to 85 c 6 storage temperature range tstg ?55 to 150 c .com .com .com .com 4 .com u datasheet
m68hc16zec20/d motorola 3 notes: 1. the average chip-junction temperature (t j ) in c can be obtained from (1): where: t a = ambient temperature, c q ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ?chip internal power p i/o = power dissipation on input and output pins ?user determined for most applications p i/o < p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is (2): solving equations (1) and (2) for k gives (3): where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . table a? typical ratings num rating symbol value unit 1 supply voltage v dd 5.0 v 2 operating temperature t a 25 c 3 v dd supply current run lpstop, vco off lpstop, external clock, max f sys i dd 113 125 3.75 ma m a ma 4 clock synthesizer operating voltage v ddsyn 5.0 v 5 v ddsyn supply current vco on, maximum f sys external clock, maximum f sys lpstop, vco off v dd powered down i ddsyn 1.0 5.0 100 50 ma ma m a m a 6 ram standby current normal ram operation standby operation i sb 7.0 40 m a m a 7 power dissipation p d 570 mw table a? thermal characteristics num characteristic symbol value unit 1 thermal resistance 1 plastic 132-pin surface mount plastic 144-pin surface mount q ja 38 49 c/w t j t a p d q ja () + = p d kt j 273 c + () + = kp d t a 273 c + ()q ja p d 2 ++ = .com .com .com .com 4 .com u datasheet
motorola m68hc16zec20/d 4 notes: 1. the base configuration of the MC68HC16Z1 requires a 32.768 khz crystal reference, and the base configuration of the m68hc16z2 requires a 4.194 mhz crystal reference. both devices can be ordered with either reference as a mask option. 2. all internal registers retain data at 0 hz. 3. assumes that stable v ddsyn is applied, and that the crystal oscillator is stable . lock time is measured from the time v dd and v ddsyn are valid until reset is released. this specification also applies to the period required for pll lock after changing the w and y frequency control bits in the synthesizer control register (syncr) while the pll is running, and to the period re- quired for the clock to lock after lpstop. 4. internal vco frequency (f vco ) is determined by syncr w and y bit values. the syncr x bit controls a divide-by-two circuit that is not in the synthesizer feedback loop. when x = 0, the divider is enabled, and f sys = f vco ? 4. when x = 1, the divider is disabled, and f sys = f vco ? 2. x must equal one when operating at maximum specified f sys . 5. this parameter is periodically sampled rather than 100% tested. 6. assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. total external resistance from the xfc pin due to external leakage must be greater than 15 m w to guarantee this specification. filter network geometry can vary depending upon operat- ing environment. 7. proper layout procedures must be followed to achieve specifications. 8. jitter is the average deviation from the programmed frequency measured over the specified in- terval at maximum f sys . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddsyn and v ss and variation in crystal oscillator frequency increase the j clk percentage for a given in- terval. when jitter is a critical constraint on control system operation, this parameter should be measured during functional testing of the final system. table a? clock control timing (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol minimum maximum unit 1 pll reference frequency range 1 MC68HC16Z1 mc68hc16z2 f ref 20 3.2 50 5.2 khz mhz 2 system frequency 2 slow on-chip pll system frequency fast on-chip pll system frequency external clock operation f sys dc 4 (f ref ) 4 (f ref ) /128 dc 20.97 20.97 20.97 20.97 mhz 3 pll lock time 1,3,5,6,7 t lpll ?0ms 4 vco frequency 4 f vco 2 (f sys max) mhz 5 limp mode clock frequency syncr x bit = 0 syncr x bit = 1 f limp f sys max /2 f sys max mhz 6 clkout jitter 1,5,6,7,8 short term (5 m s interval) long term (500 m s interval) j clk ?.0 ?.5 1.0 0.5 % .com .com .com .com 4 .com u datasheet
m68hc16zec20/d motorola 5 table a? dc characteristics (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol min max unit 1 input high voltage v ih 0.7 (v dd )v dd + 0.3 v 2 input low voltage v il v ss ?0.3 0.2 (v dd ) v 3 input hysteresis 1,2 v hys 0.5 v 4 input leakage current 3,16 v in = v dd or v ss i in ?.5 2.5 m a 5 high impedance (off-state) leakage current 4,16 v in = v dd or v ss i oz ?.5 2.5 m a 6 cmos output high voltage 5,6,16 i oh = ?0.0 m a v oh v dd ?.2 ? 7 cmos output low voltage 7,16 i ol = 10.0 m a v ol 0.2 v 8 output high voltage 6,7,16 i oh = ?.8 ma v oh v dd ?.8 ? 9 output low voltage 7,16 i ol = 1.6 ma i ol = 5.3 ma i ol = 12 ma v ol 0.4 0.4 0.4 v 10 three state control input high voltage v ihtsc 1.6 (v dd ) 9.1 v 11 data bus mode select pull-up current 8,9 v in = v il v in = v ih imsp ?5 ?20 m a 12 MC68HC16Z1v dd supply current 10,11,12 run, crystal reference lpstop, crystal reference, vco off (stsim = 0) lpstop, external clock input = max f sys i dd 140 350 5 ma m a ma 12a mc68hc16z2 v dd supply current 10,11,12 run, crystal reference lpstop, crystal reference, vco off (stsim = 0) lpstop, external clock input = max f sys i dd 140 2 10 ma ma ma 13 clock synthesizer operating voltage v ddsyn 4.75 5.25 v .com .com .com .com 4 .com u datasheet
motorola m68hc16zec20/d 6 14 MC68HC16Z1 v ddsyn supply current 6,12 vco on, crystal reference, maximum f sys external clock, maximum f sys lpstop, crystal reference, vco off (stsim = 0) v dd powered down i ddsyn 2 6 150 100 ma ma m a m a 14a mc68hc16z2 v ddsyn supply current 6,12 vco on, crystal reference, maximum f sys external clock, maximum f sys lpstop, crystal reference, vco off (stsim = 0) v dd powered down i ddsyn 2.5 8.75 2 2 ma ma ma ma 15 ram standby voltage 13 specified v dd applied v dd = v ss v sb 0.0 3.0 5.25 5.25 v 16 MC68HC16Z1ram standby current 11 normal ram operation 14 v dd > v sb ?0.5 v transient condition v sb - 0.5 v 3 v dd 3 v ss + 0.5 v standby operation 13 v dd < v ss + 0.5 v i sb 10 3 50 m a ma m a 16a mc68hc16z2ram standby current 11 normal ram operation 14 v dd > v sb ?0.5 v transient condition v sb - 0.5 v 3 v dd 3 v ss + 0.5 v standby operation 13 v dd < v ss + 0.5 v i sb 10 3 100 m a ma m a 17 MC68HC16Z1 power dissipation 15 p d 766 mw 17a mc68hc16z2 power dissipation 15 p d 831 mv table a? dc characteristics (continued) (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol min max unit .com .com .com .com 4 .com u datasheet
m68hc16zec20/d motorola 7 notes: 1. applies to: port ada[7:0] ?an[7:0] port e[7:4] ?siz[1:0], as , ds port f[7:0] ?irq[7:1], modclk port gp[7:0] ?ic4/oc5/oc1, ic[3:1], oc[4:1]/oc1 port qs[7:0] ?txd, pcs[3:1], pcs0/ss , sck, mosi, miso bkpt /dsclk, dsi/ipipe1, pai, pclk, reset , rxd, tsc extal (when pll enabled) 2. this parameter is periodically sampled rather than 100% tested. 3. applies to all input-only pins except adc pins. 4. applies to all input/output and output pins 5. does not apply to hal t and reset because they are open drain pins. does not apply to port qs[7:0] (txd, pcs[3:1], pcs0/ss , sck, mosi, miso) in wired-or mode. 6. applies to group 1, 2, 4 input/output and all output pins 7. applies to group 1, 2, 3, 4 input/output pins, bg /cs , clkout, csboo t , freeze/quot, and ipipe0 8. applies to data[15:0] 9. use of an active pulldown device is recommended. 10. total operating current is the sum of the appropriate i dd , i ddsyn , and i sb values, plus i dda . i dd values in- clude supply currents for device modules powered by v dde and v ddi pins. 11. current measured at maximum system clock frequency, all modules active. 12. the base configuration of the MC68HC16Z1 requires a 32.768 khz crystal reference, and the base configu- ration of the m68hc16z2 requires a 4.194 mhz crystal reference. both devices can be ordered with either crystal reference as a mask option. 13. the sram module will not switch into standby mode as long as v sb does not exceed v dd by more than 0.5 volts. the sram array cannot be accessed while the module is in standby mode. 14. when v sb is more than 0.3 v greater than v dd , current flows between the v stby and v dd pins, which causes standby current to increase toward the maximum transient condition specification. system noise on the v dd and v stby pin can contribute to this condition. 15. power dissipation measured at specified system clock frequency, all modules active. power dissipation can be calculated using the expression: p d = maximum v dd (i dd + i ddsyn + i sb ) + maximum v dda (i dda ) i dd includes supply currents for all device modules powered by v dde and v ddi pins. 16. input-only pins: extal, tsc, bkpt/dsclk, pai, pclk, rxd output-only pins: csboo t , bg /cs1 , clkout, freeze/quot, ds0/ipipe0, pwma, pwmb input/output pins: group 1: port gp[7:0] ?ic4/oc5/oc1, ic[3:1], oc[4:1]/oc1 data[15:0], dsi/ipipe1 group 2: port c[6:0] ?addr[22:19]/cs[9:6] , fc[2:0]/cs[5:3 ] port e[7:0] ?siz[1:0], as , ds , a vec , dsa ck[1:0] port f[7:0] ?irq[7:1] , modclk port qs[7:3] ?txd, pcs[3:1], pcs0/ss , addr23/cs10 /eclk addr[18:0], r/w , berr , br /cs0 , bga ck /cs2 group 3: hal t , reset group 4: miso, mosi, sck 18 input capacitance 3,16 all input-only pins except adc pins all input/output pins c in 10 20 pf 19 load capacitance 16 group 1 i/o pins, clkout, freeze/quot, ipipe0 group 2 i/o pins and csboo t , bg /cs group 3 i/o pins group 4 i/o pins c l 90 100 130 200 pf table a? dc characteristics (continued) (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol min max unit .com .com .com .com 4 .com u datasheet
motorola m68hc16zec20/d 8 table a? ac timing (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit f1 frequency of operation 2 MC68HC16Z1 mc68hc16z2 f 4 (f ref ) 4 (f ref )/128 20.97 20.97 mhz 1 clock period t cyc 47.7 ns 1a eclk period t ecyc 381 ns 1b external clock input period 3 t xcyc 47.7 ns 2, 3 clock pulse width t cw 18.8 ns 2a, 3a eclk pulse width t ecw 183 ns 2b, 3b external clock input high/low time 3 t xchl 23.8 ns 4, 5 clkout rise and fall time t crf ?ns 4a, 5a rise and fall time (all outputs except clkout) t rf ?ns 4b, 5b external clock input rise and fall time 4 t xcrf ?ns 6 clock high to addr, fc, size valid t chav 023ns 7 clock high to addr, data, fc, size, high impedance t chazx 047ns 8 clock high to addr, fc, size, invalid t chazn 0ns 9 clock low to as , ds , cs asserted t clsa 023ns 9a as to ds or cs asserted (read) 5 t stsa -10 10 ns 11 addr, fc, size valid to as , cs , (and ds read) asserted t avsa 10 ns 12 clock low to as , ds , cs negated t clsn 223ns 13 as , ds , cs negated to addr, fc size invalid (address hold) t snai 10 ns 14 as , cs (and ds read) width asserted t swa 80 ns 14a ds , cs width asserted (write) t swaw 36 ns 14b as , cs (and ds read) width asserted (fast cycle) t swdw 32 ns 15 as , ds , cs width negated 6 t sn 32 ns 16 clock high to as , ds , r/w high impedance t chsz ?7ns 17 as , ds , cs negated to r/w high t snrn 10 ns 18 clock high to r/w high t chrh 023ns 20 clock high to r/w low t chrl 023ns 21 r/w high to as , cs asserted t raaa 10 ns 22 r/w low to ds , cs asserted (write) t rasa 54 ns 23 clock high to data out valid t chdo ?3ns 24 data out valid to negating edge of as , cs (fast write cycle) t dvasn 10 ns 25 ds , cs negated to data out invalid (data out hold) t sndoi 10 ns 26 data out valid to ds , cs asserted (write) t dvsa 10 ns .com .com .com .com 4 .com u datasheet
m68hc16zec20/d motorola 9 27 data in valid to clock low (data setup) t dicl 5ns 27a late berr , hal t asserted to clock low (setup time) t belcl 15 ns 28 as , ds negated to dsa ck[1:0] , berr , hal t , a vec negated t sndn 060ns 29 ds , cs negated to data in invalid (data in hold) 7 t sndi 0ns 29a ds , cs negated to data in high impedance 7, 8 t shdi ?8ns 30 clkout low to data in invalid (fast cycle hold) 7 t cldi 10 ns 30a clkout low to data in high impedance 7 t cldh ?2ns 31 dsa ck[1:0] asserted to data in valid 9 t dadi ?6ns 33 clock low to bg asserted/negated t clban ?3ns 35 br asserted to bg asserted 10 t braga 1 t cyc 37 bga ck asserted to bg negated t gagn 12 t cyc 39 bg width negated t gh 2 t cyc 39a bg width asserted t ga 1 t cyc 46 r/w width asserted (write or read) t rwa 115 ns 46a r/w width asserted (fast write or read cycle) t rwas 70 ns 47a asynchronous input setup time br , bga ck , dsa ck[1:0] , berr , a vec , hal t t aist 5ns 47b asynchronous input hold time t aiht 12 ns 48 dsa ck[1:0] asserted to berr , hal t asserted 11 t daba ?0ns 53 data out hold from clock high t doch 0ns 54 clock high to data out high impedance t chdh ?3ns 55 r/w asserted to data bus impedance change t radc 32 ns 70 clock low to data bus driven (show cycle) t scldd 023ns 71 data setup time to clock low (show cycle) t sclds 10 ns 72 data hold from clock low (show cycle) t scldh 10 ns 73 bkpt input setup time t bkst 10 ns 74 bkpt input hold time t bkht 10 ns 75 mode select setup time (data[15:0], modclk , bkpt) t mss 20 t cyc 76 mode select hold time (data[15:0], modclk , bkpt) t msh 0ns 77 reset assertion time 12 t rsta 4 t cyc 78 reset rise time 13,14 t rstr ?0 t cyc table a? ac timing (continued) (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit .com .com .com .com 4 .com u datasheet
motorola m68hc16zec20/d 10 notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. 2. the base configuration of the MC68HC16Z1 requires a 32.768 khz crystal reference, and the base con- figuration of the m68hc16z2 requires a 4.194 mhz crystal reference. both devices can be ordered with either crystal reference as a mask option. 3. when an external clock is used, minimum high and low times are based on a 50% duty cycle. the mini- mum allowable t xcyc period is reduced when the duty cycle of the external clock varies. the relationship between external clock input duty cycle and minimum t xcyc is expressed: minimum t xcyc period = minimum t xchl / (50% ?external clock input duty cycle tolerance). 4. parameters for an external clock signal applied while the internal pll is disabled (modclk pin held low during reset). does not pertain to an external reference applied while the pll is enabled (modclk pin held high during reset). when the pll is enabled, the clock synthesizer detects successive transitions of the reference signal. if transitions occur within the correct clock period, rise/fall times and duty cycle are not critical. 5. specification 9a is the worst-case skew between as and ds or cs . the amount of skew depends on the relative loading of these signals. when loads are kept within specified limits, skew will not cause as and ds to fall outside the limits shown in specification 9. 6. if multiple chip selects are used, cs width negated (specification 15) applies to the time from the nega- tion of a heavily loaded chip select to the assertion of a lightly loaded chip select. the cs width negated specification between multiple chip selects does not apply to chip selects being used for synchronous eclk cycles. 7. hold times are specified with respect to ds or cs on asynchronous reads and with respect to clkout on fast cycle reads. the user is free to use either hold time. 8. maximum value is equal to (t cyc / 2) + 25 ns. 9. if the asynchronous setup time (specification 47a) requirements are satisfied, the dsa ck[1:0] low to data setup time (specification 31) and dsa ck[1:0] low to berr low setup time (specification 48) can be ig- nored. the data must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. berr must satisfy only the late berr low to clock low setup time (specification 27a) for the following clock cycle. 10. to ensure coherency during every operand transfer, bg is not asserted in response to br until after all cycles of the current operand transfer are complete. 11. in the absence of dsa ck[1:0] , berr is an asynchronous input using the asynchronous setup time (specification 47a). 12. after external reset negation is detected, a short transition period (approximately 2) t cyc elapses, then the sim drives reset low for 512 t cyc . 13. external assertion of the reset input can overlap internally-generated resets. to insure that an exter- nal reset is recognized in all cases, reset must be asserted for at least 590 clkout cycles. 14. external logic must pull reset high during this period in order for normal mcu operation to begin. 15. eight pipeline states are multiplexed into ipipe[1:0]. the multiplexed signals have two phases. 16.address access time = (2.5 + ws) t cyc ?t chav ?t dicl chip select access time = (2 + ws) t cyc ?t clsa ?t dicl where: ws = number of wait states. when fast termination is used (2 clock bus) ws = ?. 100 clkout high to phase 1 asserted 15 t chp1a 340ns 101 clkout high to phase 2 asserted 15 t chp2a 340ns 102 phase 1 valid to as or ds asserted 15 t p1vsa 10 ns 103 phase 2 valid to as or ds asserted 15 t p2vsn 10 ns 104 as or ds valid to phase 1 negated 15 t sap1n 10 ns 105 as or ds negated to phase 2 negated 15 t snp2n 10 ns table a? ac timing (continued) (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit .com .com .com .com 4 .com u datasheet
m68hc16zec20/d motorola 11 figure a? clkout output timing diagram figure a? external clock input timing diagram figure a? eclk output timing diagram 16 clkout tim 4 clkout 5 2 3 1 16 ext clk input tim 4b extal 5b 2b 3b 1b note: timing shown with respect to 20% and 70% v dd . pulse width shown with respect to 50% v dd . 16 eclk output tim 4a eclk 5a 2a 3a 1a note: timing shown with respect to 20% and 70% v dd. .com .com .com .com 4 .com u datasheet
motorola m68hc16zec20/d 12 figure a? read cycle timing diagram 16 rd cyc tim clkout s0 s1 s2 s3 s4 s5 103 105 47b 47a 102 100 101 104 48 27a 27 29a 28 20 31 29 47a 46 18 21 9a 9 11 12 13 16 8 6 addr[23:0] fc[2:0] siz[1:0] ds cs r/w as dsack0 dsack1 data[15:0] berr halt bkpt asynchronous inputs ipipe0 ipipe1 phase 1 phase 2 14 .com .com .com .com 4 .com u datasheet
m68hc16zec20/d motorola 13 figure a? write cycle timing diagram 16 wr cyc tim clkout s0 s1 s2 s3 s4 s5 48 27a 28 17 25 20 9 11 14 12 13 15 8 6 addr[23:20] fc[2:0] siz[1:0] ds cs r/w as dsack0 dsack1 data[15:0] berr halt bkpt 54 53 55 47a 46 26 23 9 74 73 103 105 102 100 101 104 ipipe0 ipipe1 phase 1 phase 2 22 14a .com .com .com .com 4 .com u datasheet
motorola m68hc16zec20/d 14 figure a? fast termination read cycle timing diagram 16 fast rd cyc tim clkout s0 s1 s4 s5 s0 18 9 6 addr[23:0] fc[2:0] siz[1:0] ds cs r/w as data[15:0] 8 bkpt 12 46a 30 29a 20 74 30a 29 phase 1 phase 2 100 102 104 103 105 101 ipipe0 ipipe1 27 73 14b .com .com .com .com 4 .com u datasheet
m68hc16zec20/d motorola 15 figure a? fast termination write cycle timing diagram clkout s0 s1 s4 s5 s0 20 9 6 addr[23:0] fc[1:0] siz[1:0] ds cs r/w as data[15:0] 14b 8 bkpt 100 101 ipipe0 ipipe1 phase 1 12 46a 23 27a phase 2 24 18 25 16 fast wr cyc tim 105 102 104 103 .com .com .com .com 4 .com u datasheet
motorola m68hc16zec20/d 16 figure a? bus arbitration timing diagram ?active bus case 16 bus arb tim clkout s0 s1 s2 s3 s4 addr[23:0] data[15:0] 7 s98 a5 a5 a2 39a 35 33 33 16 s5 as ds r/w dsack0 dsack1 br bg bgack 37 phase 1 phase 2 100 102 104 103 105 101 ipipe0 ipipe1 47a .com .com .com .com 4 .com u datasheet
m68hc16zec20/d motorola 17 figure a? bus arbitration timing diagram ?idle bus case figure a?0 show cycle timing diagram 16 bus arb tim idle clkout a0 a5 addr[23:0] data[15:0] a2 a3 a0 a5 br as bg bgack 47a 33 33 47a 37 47a 35 clkout s0 s41 s42 s0 s1 s2 6 addr[23:0] r/w as 8 ds 72 data[15:0] bkpt 71 70 12 9 15 18 20 show cycle start of external cycle 74 s43 16 shw cyc tim phase 1 phase 2 phase 1 phase 2 100 102 104 103 105 101 73 ipipe0 ipipe1 note: show cycles can stretch during clock phase s42 when bus accesses take longer than two cycles due to imb module wait-state insertion. .com .com .com .com 4 .com u datasheet
motorola m68hc16zec20/d 18 figure a?1 chip-select timing diagram figure a?2 reset and mode select timing diagram table a? background debugging mode timing (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit b0 dsi input setup time t dsisu 15 ns 16 chip sel tim 6 6 8 11 11 25 53 54 23 55 29a 29 27 46 46 14a 12 13 15 9 9 12 14 9 18 20 18 s0 s1 s2 s3 s4 s5 s0 s1 s2 s3 s4 s5 14 clkout addr[23:0] fc[2:0] siz[1:0] as ds cs r/w data[15:0] 21 17 17 16 rst/mode sel tim reset data[15:0], 75 76 77 78 modclk, bkpt .com .com .com .com 4 .com u datasheet
m68hc16zec20/d motorola 19 figure a?3 bdm serial communication timing diagram figure a?4 bdm freeze assertion timing diagram notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. b1 dsi input hold time t dsih 10 ns b2 dsclk setup time t dscsu 15 ns b3 dsclk hold time t dsch 10 ns b4 dso delay time t dsod ?5ns b5 dsclk cycle time t dsccyc 2 t cyc b6 clkout low to freeze asserted/negated t frzan ?0ns b7 clkout high to ipipe1 high impedance t ipz ?0ns b8 clkout high to ipipe1 valid t ip ?0ns b9 dsclk low time t dsclo 1 t cyc b10 ipipe1 high impedance to freeze asserted t ipfa tbd t cyc b11 freeze negated to ipipe[0:1] active t frip tbd t cyc table a? background debugging mode timing (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit 16 bdm ser com tim b1 b3 b2 b0 b4 clkout freeze bkpt /dsclk ipipe1/dsi ipipe0/dso b5 b9 16 bdm frz tim b8 clkout freeze ipipe1/dsi b6 b7 b11 b6 b10 .com .com .com .com 4 .com u datasheet
motorola m68hc16zec20/d 20 figure a?5 eclk timing diagram notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. 2. when previous bus cycle is not an eclk cycle, the address may be valid before eclk goes low. 3. address access time = t ecyc ?t ead ?t edsr . 4. chip select access time = t ecyc ?t ecsd ?t edsr . table a? eclk bus timing (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit e1 eclk low to address valid 2 t ead ?8ns e2 eclk low to address hold teah 10 ns e3 eclk low to cs valid (cs delay) tecsd 120 ns e4 eclk low to cs hold tecsh 10 ns e5 cs negated width tecsn 25 ns e6 read data setup time tedsr 25 ns e7 read data hold time tedhr 5ns e8 eclk low to data high impedance tedhz ?8ns e9 cs negated to data hold (read) tecdh 0ns e10 cs negated to data high impedance tecdz ? t cyc e11 eclk low to data valid (write) teddw ? t cyc e12 eclk low to data hold (write) tedhw 10 ns e13 address access time (read) 3 teacc 308 ns e14 chip-select access time (read) 4 teacs 236 ns e15 address setup time teas 1/2 t cyc hc16 e cycle tim clkout addr[23:0] cs eclk data[15:0] e1 2a 3a e2 e5 e4 e3 e9 e7 e8 e10 e12 e14 e13 1a data[15:0] e15 e11 write read write e6 r/w .com .com .com .com 4 .com u datasheet
m68hc16zec20/d motorola 21 notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. 2. for high time, n = external sck rise time; for low time, n = external sck fall time. table a? qspi timing (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h , 200 pf load on all qspi pins) 1 num function symbol min max unit 1 operating frequency master slave f op dc dc 1/4 1/4 f sys f sys 2 cycle time master slave t qcyc 4 4 510 t cyc t cyc 3 enable lead time master slave t lead 2 2 128 t cyc t cyc 4 enable lag time master slave t lag 2 1/2 sck t cyc 5 clock (sck) high or low time master slave 2 t sw 2 t cyc ?60 2 t cyc ?n 255 t cyc ns ns 6 sequential transfer delay master slave (does not require deselect) t td 17 13 8192 t cyc t cyc 7 data setup time (inputs) master slave t su 30 20 ns ns 8 data hold time (inputs) master slave t hi 0 20 ns ns 9 slave access time t a ? t cyc 10 slave miso disable time t dis ? t cyc 11 data valid (after sck edge) master slave t v 50 50 ns ns 12 data hold time (outputs) master slave t ho 0 0 ns ns 13 rise time input output t ri t ro 2 30 m s ns 14 fall time input output t fi t fo 2 30 m s ns .com .com .com .com 4 .com u datasheet
motorola m68hc16zec20/d 22 figure a?6 qspi timing ?master, cpha = 0 figure a?7 qspi timing ?master, cpha = 1 16 qspi mast cpha0 13 11 6 10 12 4 4 13 12 3 2 5 1 data lsb in msb in msb out msb in msb out data lsb out port data 7 12 13 pcs[3:0] output pd miso input mosi output sck cpol=0 output sck cpol=1 output 16 qspi mast cpha1 13 11 10 12 4 4 13 12 3 2 5 1 msb pcs[3:0] output miso input msb msb out data lsb out port data 12 13 port data mosi output data lsb in msb in 7 6 1 sck cpol=0 output sck cpol=1 output .com .com .com .com 4 .com u datasheet
m68hc16zec20/d motorola 23 figure a?8 qspi timing ?slave, cpha = 0 figure a?9 qspi timing ?slave, cpha = 1 13 10 13 7 6 8 11 9 11 12 4 13 12 3 2 5 1 data lsb out pd msb out msb in msb out msb in data lsb in ss input sck cpol=0 input sck cpol=1 input miso output mosi input 4 16 qspi slv cpha0 16 qspi slv cpha1 ss input 13 12 4 12 5 11 12 6 10 9 8 data slave lsb out pd msb out msb in data lsb in 7 4 1 2 10 pd 13 3 miso output sck cpol=1 input mosi input sck cpol=0 input .com .com .com .com 4 .com u datasheet
motorola m68hc16zec20/d 24 notes: 1. below disruptive current conditions, a stressed channel will store the maximum conversion value for analog inputs greater than v rh and the minimum conversion value for inputs less than v rl . this as- sumes that v rh v dda and v rl 3 v ssa due to the presence of the sample amplifier. other channels are not affected by non-disruptive conditions 2. input signals with large slew rates or high frequency noise components cannot be converted accurate- ly. these signals also interfere with conversion of other channels. 3. exceeding limit may cause conversion error on stressed channels and on unstressed channels. transi- tions within the limit do not affect device reliability or cause permanent damage. 4. input must be current limited to the value specified. to determine the value of the required current-lim- iting resistor, calculate resistance values using positive and negative clamp values, then use the larger of the calculated values. 5. this parameter is periodically sampled rather than 100% tested. 6. applies to single pin only. 7. the values of external system components can change the maximum input current value, and affect operation. a voltage drop may occur across the external source impedances of the adjacent pins, im- pacting conversions on these adjacent pins. the actual maximum may need to be determined by test- ing the complete design. 8. current coupling is the ratio of the current induced from overvoltage (positive or negative, through an external series coupling resistor), divided by the current induced on adjacent pins. a voltage drop may occur across the external source impedances of the adjacent pins, impacting conversions on these ad- jacent pins table a?0 adc maximum ratings num parameter symbol min max unit 1 analog supply v dda ?.3 6.5 v 2 internal digital supply, with reference to v ssi v ddi ?.3 6.5 v 3 reference supply, with reference to v ssi v rh , v rl ?.3 6.5 v 4 v ss differential voltage v ssi ? ssa ?.1 0.1 v 5 v dd differential voltage v ddi ? dda ?.5 6.5 v 6 v ref differential voltage v rh ? rl ?.5 6.5 v 7 v rh to v dda differential voltage v rh ? dda ?.5 6.5 v 8 v rl to v ssa differential voltage v rl ? ssa ?.5 6.5 v 9 disruptive input current 1 , 2 , 3 , 4 , 5 , 6 , 7 v negclamp @ ?.3 v v posclamp @ 8 v i na ?00 500 m a 10 positive overvoltage current coupling ratio 1,5,6, 8 k p 2000 11 negative overvoltage current coupling ratio 1,5,6 ,8 k n 500 12 maximum input current 3,4,6 v negclamp @ ?.3 v v posclamp @ 8 v i ma ?5 25 ma .com .com .com .com 4 .com u datasheet
m68hc16zec20/d motorola 25 notes: 1. refers to operation over full temperature and frequency range. 2. to obtain full-scale, full-range results, v ssa v rl v indc v rh v dda. 3. accuracy tested and guaranteed at v rh ?v rl = 5.0 v 5%. 4. current measured at maximum system clock frequency with adc active. 5. maximum leakage occurs at maximum operating temperature. current decreases by approximately one-half for each 10 c decrease from maximum temperature. table a?1 adc dc electrical characteristics (operating) (v ss = 0 vdc, adclk = 2.1 mhz, t a = t l to t h ) num parameter symbol min max unit 1 analog supply 1 v dda 4.5 5.5 v 2 internal digital supply 1 v ddi 4.5 5.5 v 3 v ss differential voltage v ssi ? v ssa ?1.0 1.0 mv 4 v dd differential voltage v ddi v dda ?1.0 1.0 v 5 reference voltage low 2,3 v rl v ssa v dda / 2 v 6 reference voltage high 2,3 v rh v dda / 2 v dda v 7 v ref differential voltage 3 v rh v rl 4.5 5.5 v 8 input voltage 2 v indc v ssa v dda v 9 input high, port ada v ih 0.7 (v dda )v dda + 0.3 v 10 input low, port ada v il v ssa 0.3 0.2 (v dda ) v 11 analog supply current normal operation 4 low-power stop i dda 1.0 200 ma m a 12 reference supply current i ref 250 m a 13 input current, off channel 5 i off 150 na 14 total input capacitance, not sampling c inn ?0pf 15 total input capacitance, sampling c i ns ?5pf .com .com .com .com 4 .com u datasheet
motorola m68hc16zec20/d 26 notes: 1. conversion accuracy varies with f adclk rate. reduced conversion accuracy occurs at maximum. notes: 1. at v rh ? rl = 5.12 v, one 10-bit count = 5 mv and one 8-bit count = 20 mv. 2. 8-bit absolute error of 1 count (20 mv) includes 1/2 count (10 mv) inherent quantization error and 1/2 count (10 mv) circuit (differential, integral, and offset) error. 3. conversion accuracy varies with f adclk rate. reduced conversion accuracy occurs at maximum f ad- clk . assumes that minimum sample time (2 adc clocks) is selected. 4. 10-bit absolute error of 2.5 counts (12.5 mv) includes 1/2 count (2.5 mv) inherent quantization error and 2 counts (10 mv) circuit (differential, integral, and offset) error. 5. maximum source impedance is application-dependent. error resulting from pin leakage depends on junction leakage into the pin and on leakage due to charge-sharing with internal capacitance. error from junction leakage is a function of external source impedance and input leakage current. ex- pected error in result value due to junction leakage is expressed in voltage (v errj ): v errj = r s x i off where i off is a function of operating temperature, as shown in table a?1. charge-sharing leakage is a function of input source impedance, conversion rate, change in voltage between successive conversions, and the size of the decoupling capacitor used. error levels are best determined empirically. in general, continuous conversion of the same channel may not be compatible with high source impedance. table a?2 adc ac characteristics (operating) (v dd and v dda = 5.0 vdc 5%, v ss = 0 vdc, t a within operating temperature range) num parameter symbol min max unit 1 adc clock frequency f adclk 0.5 2.1 mhz 2 8-bit conversion time 1 f adclk = 1.0 mhz f adcl k = 2.1 mhz t conv 15.2 7.6 m s 3 10-bit conversion time 1 f adclk = 1.0 mhz f adclk = 2.1 mhz t conv 17.1 8.6 m s 4 stop recovery time t sr ?0 m s table a?3 adc conversion characteristics (operating) (v dd and v dda = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h , 0.5 mhz f adclk 1.0 mhz, 2 clock input sample time) num parameter symbol min typical max unit 1 8-bit resolution 1 1 count 20 mv 2 8-bit differential nonlinearity dnl ?.5 0.5 counts 3 8-bit integral nonlinearity inl ? 1 counts 4 8-bit absolute error 2 ae ? 1 counts 5 10-bit resolution 1 1 count 5 mv 6 10-bit differential nonlinearity 3 dnl ?.5 0.5 counts 7 10-bit integral nonlinearity 3 inl ?.0 2.0 counts 8 10-bit absolute error 3,4 ae ?.5 2.5 counts 9 source impedance at input 5 r s ?0k w .com .com .com .com 4 .com u datasheet
m68hc16zec20/d motorola 27 figure a?0 8-bit adc conversion accuracy figure a?1 10-bit adc conversion accuracy adc 8-bit accuracy 0 204060 input in mv, v rh ?v rl = 5.120 v -20 mv 8-bit absolute error boundary +20 mv 8-bit absolute error boundary b c ideal transfer curve 8-bit transfer curve (no circuit error) digital output a a b c ? +1/2 count (10 mv) inherent quantization error ? circuit-contributed +10mv error ? + 20 mv absolute error (one 8-bit count) adc 10-bit accuracy 0 204060 input in mv, v rh ?v rl = 5.120 v c a b +12.5 mv 10-bit absolute error boundary 10-bit transfer curve (no circuit error) ideal transfer curve digital output a b c ? +.5 count (2.5 mv) inherent quantization error ?circuit-contributed +10 mv error ?+12.5 mv absolute error (2.5 10-bit counts) -12.5 mv 10-bit absolute error boundary .com .com .com .com 4 .com u datasheet
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order this document by: m68hc16zec25/d ?motorola inc, 1995 semiconductor motorola technical data MC68HC16Z1 technical supplement 25.17 mhz electrical characteristics devices in the m68hc16 modular microcontroller family are built up from a selection of standard functional modules. published electrical characteristics for MC68HC16Z1 devices are based on a16.78 mhz system clock. new products that operate at clock frequencies of 25.17 mhz are now available. this supplement consists of a new electrical characteristics appendix (appendix a) that supplements those published in the MC68HC16Z1 user's manual (MC68HC16Z1um/ad). the supplement contains the following updated specifications: table page maximum ratings ...................................................................................................... 2 typical ratings .......................................................................................................... 3 thermal characteristics ............................................................................................. 3 clock control timing ................................................................................................. 4 dc characteristics ..................................................................................................... 5 ac timing ................................................................................................................. 7 background debugging mode timing .................................................................... 18 eclk bus timing ................................................................................................... 19 qspi timing ............................................................................................................ 20 adc maximum ratings ........................................................................................... 23 adc dc electrical characteristics (operating) ....................................................... 24 adc ac characteristics (operating) ...................................................................... 24 adc conversion characteristics (operating) .......................................................... 25 .com .com .com .com 4 .com u datasheet
motorola m68hc16zec25/d 2 notes: 1. permanent damage can occur if maximum ratings are exceeded. exposure to voltag- es or currents in excess of recommended values affects device reliability. device mod- ules may not operate normally while being exposed to electrical extremes. 2. although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields, take normal precautions to avoid exposure to voltag- es higher than maximum-rated voltages. 3. this parameter is periodically sampled rather than 100% tested. 4. all pins except tsc. 5. input must be current limited to the value specified. to determine the value of the re- quired current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 6. power supply must maintain regulation within operating v dd range during instanta- neous and operating maximum current. 7. all functional non-supply pins are internally clamped to v ss . all functional pins except extal and xfc are internally clamped to v dd . 8. total input current for all digital input-only and all digital input/output pins must not ex- ceed 10 ma. exceeding this limit can cause disruption of normal operation. table a? maximum ratings num rating symbol value unit 1 supply voltage 1, 2, 3 v dd ?0.3 to + 6.5 v 2 input voltage 1, 2, 3, 4, 5,7 v in ?0.3 to + 6.5 v 3 instantaneous maximum current single pin limit (all pins) 1, 3, 5, 6 i d 25 ma 4 operating maximum current digital input disruptive current 3, 5, 6, 7, 8 v negclmap @ ?0.3 v v posclamp @ v dd + 0.3 ii d ?500 to 500 m a 5 operating temperature range ??suffix ??suffix ??suffix t a tl to th ?40 to 85 ?40 to 105 ?40 to 125 c 6 storage temperature range t stg ?55 to 150 c .com .com .com .com 4 .com u datasheet
m68hc16zec25/d motorola 3 notes: 1. the average chip-junction temperature (tj) in c can be obtained from (1): where: t a = ambient temperature, c q ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ?chip internal power p i/o = power dissipation on input and output pins ?user determined for most applications p i/o < p int and can be neglected. an approximate relation- ship between p d and t j (if p i/o is neglected) is (2): solving equations (1) and (2) for k gives (3): where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring pd (at equilibrium) for a known ta. using this value of k, the values of pd and tj can be obtained by solving equations (1) and (2) itera- tively for any value of ta. table a? typical ratings num rating symbol value unit 1 supply voltage v dd 5.0 v 2 operating temperature t a 25 c 3 v dd supply current run lpstop, vco off lpstop, external clock, max f sys i dd 113 125 3.75 ma m a ma 4 clock synthesizer operating voltage v ddsyn 5.0 v 5 v ddsyn supply current vco on, maximum f sys external clock, maximum f sys lpstop, vco off v dd powered down i ddsyn 1.0 5.0 100 50 ma ma m a m a 6 ram standby voltage v sb 3.0 v 7 ram standby current normal ram operation standby operation isb 7.0 40 m a m a 8 power dissipation p d 570 mw table a? thermal characteristics num characteristic symbol value unit 1 thermal resistance 1 plastic 132-pin surface mount plastic 144-pin surface mount q ja 38 49 c/w t j t a p d q ja () + = p d kt j 273 c + () + = kp d t a 273 c + ()q ja p d 2 ++ = .com .com .com .com 4 .com u datasheet
motorola m68hc16zec25/d 4 notes: 1. tested with a 32.768 khz reference. 2. all internal registers retain data at 0 hz. 3. assumes that stable v ddsyn is applied, and that the crystal oscillator is stable . lock time is measured from the time v dd and v ddsyn are valid until reset is released. this specifica- tion also applies to the period required for pll lock after changing the w and y frequency control bits in the synthesizer control register (syncr) while the pll is running, and to the period required for the clock to lock after lpstop. 4. internal vco frequency (f vco ) is determined by syncr w and y bit values. the syncr x bit controls a divide-by-two circuit that is not in the synthesizer feedback loop. when x = 0, the divider is enabled, and f sys = f vco ? 4. when x = 1, the divider is disabled, and f sys = f vco ? 2. x must equal one when operating at maximum specified f sys . 5. this parameter is periodically sampled rather than 100% tested. 6. assumes that a low-leakage external filter network is used to condition clock synthesizer in- put voltage. total external resistance from the xfc pin due to external leakage must be greater than 15 m w to guarantee this specification. filter network geometry can vary de- pending upon operating environment. 7. proper layout procedures must be followed to achieve specifications. 8. jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f sys . measurements are made with the device powered by filtered sup- plies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddsyn and v ss and variation in crystal oscillator frequency increase the j clk percentage for a given interval. when jitter is a critical constraint on control system operation, this param- eter should be measured during functional testing of the final system. table a? clock control timing (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h , stable external reference ) 1 num characteristic symbol minimum maximum unit 1 pll reference frequency range f ref 25 50 khz 2 system frequency 2 on-chip pll system frequency external clock operation f sys dc 0.131 dc 25.17 25.17 25.17 mhz 3 pll lock time 3,5,6,7 t lpll ?0ms 4 vco frequency 4 f vco 2 (f sys max) mhz 5 limp mode clock frequency syncr x bit = 0 syncr x bit = 1 f limp f sys max /2 f sys max mhz 6 clkout jitter 5,6,7,8 short term (5 m s interval) long term (500 m s interval) j clk ?.0 ?.5 1.0 0.5 % .com .com .com .com 4 .com u datasheet
m68hc16zec25/d motorola 5 table a? dc characteristics (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol min max unit 1 input high voltage v ih 0.7 (v dd )v dd + 0.3 v 2 input low voltage v il v ss ?0.3 0.2 (v dd ) v 3 input hysteresis 1, 2 v hys 0.5 v 4 input leakage current 3,16 v in = v dd or v ss i in ?2.5 2.5 m a 5 high impedance (off-state) leakage current 4,16 v in = v dd or v ss i oz ?2.5 2.5 m a 6 cmos output high voltage 5,6,16 i oh = ?0.0 m a v oh v dd ?0.2 ? 7 cmos output low voltage 6,16 i ol = 10.0 m a v ol 0.2 v 8 output high voltage 5,6,16 i oh = ?.8 ma v oh v dd ?.8 ? 9 output low voltage 7,16 i ol = 1.6 ma i ol = 5.3 ma i ol = 12 ma v ol 0.4 0.4 0.4 v 10 three state control input high voltage v ihtsc 1.6 (v dd ) 9.1 v 11 data bus mode select pull-up current 8,9 v in = v il v in = v ih i msp ?5 ?20 m a 12 v dd supply current 10,11, 12 run lpstop, crystal reference, vco off (stsim = 0) lpstop, external clock input frequency = maximum f sys i dd 140 350 5 ma m a m a 13 clock synthesizer operating voltage v ddsyn 4.75 5.25 v 14 v ddsyn supply current 6,12 crystal reference, vco on, maximum f sys external clock input, maximum f sys crystal reference, lpstop, vco off (stsim = 0) crystal reference, v dd powered down i ddsyn 2 7 150 100 ma ma m a m a 15 ram standby voltage 13 specified v dd applied v dd = v ss v sb 0.0 3.0 5.25 5.25 v 16 ram standby current 10 normal ram operation 14 v dd > v sb ?0.5 v transient condition v sb - 0.5 v 3 v dd 3 v ss + 0.5 v standby operation 13 v dd < v ss + 0.5 v i sb 10 3 50 m a ma m a 17 power dissipation 15, 16 p d 766 mw 18 input capacitance 2, 16 all input-only pins except adc pins all input/output pins c in 10 20 pf .com .com .com .com 4 .com u datasheet
motorola m68hc16zec25/d 6 notes: 1. applies to: port ada[7:0] ?an[7:0] port e[7:4] ?siz[1:0], as , ds port f[7:0] ?irq[7:1], modclk port gp[7:0] ?ic4/oc5/oc1, ic[3:1], oc[4:1]/oc1 port qs[7:0] ?txd, pcs[3:1], pcs0/ss , sck, mosi, miso bkpt /dsclk, dsi/ipipe1, pai, pclk, reset , rxd, tsc extal (when pll enabled) 2. this parameter is periodically sampled rather than 100% tested. 3. applies to all input-only pins except adc pins. 4. applies to all input/output and output pins 5. does not apply to hal t and reset because they are open drain pins. does not apply to port qs[7:0] (txd, pcs[3:1], pcs0/ss , sck, mosi, miso) in wired-or mode. 6. applies to group 1, 2, 4 input/output and all output pins 7. applies to group 1, 2, 3, 4 input/output pins, bg /cs , clkout, csboo t , freeze/quot, and ipipe0 8. applies to data[15:0] 9. use of an active pulldown device is recommended. 10. total operating current is the sum of the appropriate i dd , i ddsyn , and i sb values, plus i dda . i dd val- ues include supply currents for device modules powered by v dde and v ddi pins. 11. current measured at maximum system clock frequency, all modules active. 12. tested with a 32.768 khz crystal reference. 13. the sram module will not switch into standby mode as long as v sb does not exceed v dd by more than 0.5 volts. the sram array cannot be accessed while the module is in standby mode. 14. when v sb is more than 0.3 v greater than v dd , current flows between the v stby and v dd pins, which causes standby current to increase toward the maximum transient condition specification. system noise on the v dd and v stby pin can contribute to this condition. 15. power dissipation measured at specified system clock frequency, all modules active. power dissipation can be calculated using the expression: p d = maximum v dd (i dd + i ddsyn + i sb ) + maximum v dda (i dda ) i dd includes supply currents for all device modules powered by v dde and v ddi pins. 16. input-only pins: extal, tsc, bkpt/dsclk, pai, pclk, rxd output-only pins: csboo t , bg /cs1 , clkout, freeze/quot, ds0/ipipe0, pwma, pwmb input/output pins: group 1: port gp[7:0] ?ic4/oc5/oc1, ic[3:1], oc[4:1]/oc1 data[15:0], dsi/ipipe1 group 2: port c[6:0] ?addr[22:19]/cs[9:6] , fc[2:0]/cs[5:3 ] port e[7:0] ?siz[1:0], as , ds , a vec , dsa ck[1:0] port f[7:0] ?irq[7:1] , modclk port qs[7:3] ?txd, pcs[3:1], pcs0/ss , addr23/cs10 /eclk addr[18:0], r/w , berr , br /cs0 , bga ck /cs2 group 3: hal t , reset group 4: miso, mosi, sck 19 load capacitance 16 group 1 i/o pins, clkout, freeze/quot, ipipe0 group 2 i/o pins and csboo t , bg /cs group 3 i/o pins group 4 i/o pins c l 90 100 130 200 pf table a? dc characteristics (continued) (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol min max unit .com .com .com .com 4 .com u datasheet
m68hc16zec25/d motorola 7 table a? ac timing (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit f1 frequency of operation 2 f 4 (f ref ) 25.166 mhz 1 clock period t cyc 39.7 ns 1a eclk period t ecyc 318 ns 1b external clock input period 3 t xcyc 39.7 ns 2, 3 clock pulse width t cw 15 ns 2a, 3a eclk pulse width t ecw 155 ns 2b, 3b external clock input high/low time 3 t xchl 19.8 ns 4, 5 clkout rise and fall time t crf ?ns 4a, 5a rise and fall time (all outputs except clkout) t rf ?ns 4b, 5b external clock input rise and fall time 4 t xcrf ?ns 6 clock high to addr, fc, size valid t chav 019ns 7 clock high to addr, data, fc, size, high impedance t chazx 039ns 8 clock high to addr, fc, size, invalid t chazn 0ns 9 clock low to as , ds , cs asserted t clsa 219ns 9a as to ds or cs asserted (read) 5 t stsa ?0 15 ns 11 addr, fc, size valid to as , cs , (and ds read) asserted t avsa 8ns 12 clock low to as , ds , cs negated t clsn 219ns 13 as , ds , cs negated to addr, fc size invalid (address hold) t snai 8ns 14 as , cs (and ds read) width asserted t swa 65 ns 14a ds , cs width asserted (write) t swaw 25 ns 14b as , cs (and ds read) width asserted (fast cycle) t swdw 22 ns 15 as , ds , cs width negated 6 t sn 22 ns 16 clock high to as , ds , r/w high impedance t chsz ?9ns 17 as , ds , cs negated to r/w high t snrn 10 ns 18 clock high to r/w high t chrh 019ns 20 clock high to r/w low t chrl 019ns 21 r/w high to as , cs asserted t raaa 10 ns 22 r/w low to ds , cs asserted (write) t rasa 40 ns 23 clock high to data out valid t chdo ?9ns 24 data out valid to negating edge of as , cs (fast write cycle) t dvasn 7ns 25 ds , cs negated to data out invalid (data out hold) t sndoi 5ns 26 data out valid to ds , cs asserted (write) t dvsa 8ns .com .com .com .com 4 .com u datasheet
motorola m68hc16zec25/d 8 27 data in valid to clock low (data setup) t dicl 5ns 27a late berr , hal t asserted to clock low (setup time) t belcl 10 ns 28 as , ds negated to dsa ck[1:0] , berr , hal t , a vec negated t sndn 050ns 29 ds , cs negated to data in invalid (data in hold) 7 t sndi 0ns 29a ds , cs negated to data in high impedance 7, 8 t shdi ?5ns 30 clkout low to data in invalid (fast cycle hold) 7 t cldi 8ns 30a clkout low to data in high impedance 7 t cldh ?0ns 31 dsa ck[1:0] asserted to data in valid 9 t dadi ?5ns 33 clock low to bg asserted/negated t clban ?9ns 35 br asserted to bg asserted 10 t braga 1 t cyc 37 bga ck asserted to bg negated t gagn 12 t cyc 39 bg width negated t gh 2 t cyc 39a bg width asserted t ga 1 t cyc 46 r/w width asserted (write or read) t rwa 90 ns 46a r/w width asserted (fast write or read cycle) t rwas 55 ns 47a asynchronous input setup time br , bga ck , dsa ck[1:0] , berr , a vec , hal t t aist 5ns 47b asynchronous input hold time t aiht 10 ns 48 dsa ck[1:0] asserted to berr , hal t asserted 11 t daba ?7ns 53 data out hold from clock high t doch 0ns 54 clock high to data out high impedance t chdh ?3ns 55 r/w asserted to data bus impedance change t radc 25 ns 70 clock low to data bus driven (show cycle) t scldd 019ns 71 data setup time to clock low (show cycle) t sclds 8ns 72 data hold from clock low (show cycle) t scldh 8ns 73 bkpt input setup time t bkst 10 ns 74 bkpt input hold time t bkht 10 ns 75 mode select setup time (data[15:0], modclk , bkpt) t mss 20 t cyc 76 mode select hold time (data[15:0], modclk , bkpt) t msh 0ns 77 reset assertion time 12 t rsta 4 t cyc 78 reset rise time 13,14 t rstr ?0 t cyc table a? ac timing (continued) (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit .com .com .com .com 4 .com u datasheet
m68hc16zec25/d motorola 9 notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. 2. minimum system clock frequency is four times the crystal frequency, subject to specified limits. 3. when an external clock is used, minimum high and low times are based on a 50% duty cycle. the mini- mum allowable t xcyc period is reduced when the duty cycle of the external clock varies. the relationship between external clock input duty cycle and minimum t xcyc is expressed: minimum t xcyc period = minimum t xchl / (50% ?external clock input duty cycle tolerance). 4. parameters for an external clock signal applied while the internal pll is disabled (modclk pin held low during reset). does not pertain to an external vco reference applied while the pll is enabled (modclk pin held high during reset). when the pll is enabled, the clock synthesizer detects succes- sive transitions of the reference signal. if transitions occur within the correct clock period, rise/fall times and duty cycle are not critical. 5. specification 9a is the worst-case skew between as and ds or cs . the amount of skew depends on the relative loading of these signals. when loads are kept within specified limits, skew will not cause as and ds to fall outside the limits shown in specification 9. 6. if multiple chip selects are used, cs width negated (specification 15) applies to the time from the nega- tion of a heavily loaded chip select to the assertion of a lightly loaded chip select. the cs width negated specification between multiple chip selects does not apply to chip selects being used for synchronous eclk cycles. 7. hold times are specified with respect to ds or cs on asynchronous reads and with respect to clkout on fast cycle reads. the user is free to use either hold time. 8. maximum value is equal to (t cyc / 2) + 25 ns. 9. if the asynchronous setup time (specification 47a) requirements are satisfied, the dsa ck[1:0] low to data setup time (specification 31) and dsa ck[1:0] low to berr low setup time (specification 48) can be ignored. the data must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. berr must satisfy only the late berr low to clock low setup time (specification 27a) for the following clock cycle. 10. to ensure coherency during every operand transfer, bg is not asserted in response to br until after all cycles of the current operand transfer are complete. 11. in the absence of dsa ck[1:0] , berr is an asynchronous input using the asynchronous setup time (specification 47a). 12. after external reset negation is detected, a short transition period (approximately 2 t cyc ) elapses, then the sim drives reset low for 512 tcyc. 13. external assertion of the reset input can overlap internally-generated resets. to insure that an exter- nal reset is recognized in all cases, reset must be asserted for at least 590 clkout cycles. 14. external logic must pull reset high during this period in order for normal mcu operation to begin. 15. eight pipeline states are multiplexed into ipipe[1:0]. the multiplexed signals have two phases. 16.address access time = (2.5 + ws) t cyc ?t chav ?t dicl chip select access time = (2 + ws) t cyc ?t clsa ?t dicl where: ws = number of wait states. when fast termination is used (2 clock bus) ws = ?. 100 clkout high to phase 1 asserted 15 t chp1a 334ns 101 clkout high to phase 2 asserted 15 t chp2a 334ns 102 phase 1 valid to as or ds asserted 15 t p1vsa 9ns 103 phase 2 valid to as or ds asserted 15 t p2vsn 9ns 104 as or ds valid to phase 1 negated 15 t sap1n 9ns 105 as or ds negated to phase 2 negated 15 t snp2n 9ns table a? ac timing (continued) (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit .com .com .com .com 4 .com u datasheet
motorola m68hc16zec25/d 10 figure a? clkout output timing diagram figure a? external clock input timing diagram figure a? eclk output timing diagram 16 clkout tim 4 clkout 5 2 3 1 note: timing shown with respect to 20% and 70% v dd 16 ext clk input tim 4b extal 5b 2b 3b 1b note: timing shown with respect to 20% and 70% v dd pulse width shown with respect to 50% v dd 16 eclk output tim 4a eclk 5a 2a 3a 1a note: timing shown with respect to 20% and 70% v dd .com .com .com .com 4 .com u datasheet
m68hc16zec25/d motorola 11 figure a? read cycle timing diagram 16 rd cyc tim clkout s0 s1 s2 s3 s4 s5 103 105 47b 47a 102 100 101 104 48 27a 27 29a 28 20 31 29 47a 46 18 21 9a 9 11 12 13 16 8 6 addr[23:0] fc[2:0] siz[1:0] ds cs r/w as dsack0 dsack1 data[15:0] berr halt bkpt asynchronous inputs ipipe0 ipipe1 phase 1 phase 2 14 .com .com .com .com 4 .com u datasheet
motorola m68hc16zec25/d 12 figure a? write cycle timing diagram 16 wr cyc tim clkout s0 s1 s2 s3 s4 s5 48 27a 28 17 25 20 9 11 14 12 13 15 8 6 addr[23:20] fc[2:0] siz[1:0] ds cs r/w as dsack0 dsack1 data[15:0] berr halt bkpt 54 53 55 47a 46 26 23 9 74 73 103 105 102 100 101 104 ipipe0 ipipe1 phase 1 phase 2 22 14a .com .com .com .com 4 .com u datasheet
m68hc16zec25/d motorola 13 figure a? fast termination read cycle timing diagram clkout s0 s1 s4 s5 s0 18 9 6 addr[23:0] fc[2:0] siz[1:0] ds cs r/w as data[15:0] 8 bkpt 12 46a 30 29a 20 74 30a 29 phase 1 phase 2 100 102 104 103 105 101 ipipe0 ipipe1 27 73 14b 16 fast rd cyc tim .com .com .com .com 4 .com u datasheet
motorola m68hc16zec25/d 14 figure a? fast termination write cycle timing diagram clkout s0 s1 s4 s5 s0 20 9 6 addr[23:0] fc[1:0] siz[1:0] ds cs r/w as data[15:0] 14b 8 bkpt 100 101 ipipe0 ipipe1 phase 1 12 46a 23 27a phase 2 24 18 25 16 fast wr cyc tim 105 102 104 103 .com .com .com .com 4 .com u datasheet
m68hc16zec25/d motorola 15 figure a? bus arbitration timing diagram ?active bus case 16 bus arb tim clkout s0 s1 s2 s3 s4 addr[23:0] data[15:0] 7 s98 a5 a5 a2 47a 39a 35 33 33 16 s5 as ds r/w dsack0 dsack1 br bg bgack 37 phase 1 phase 2 100 102 104 103 105 101 ipipe0 ipipe1 .com .com .com .com 4 .com u datasheet
motorola m68hc16zec25/d 16 figure a? bus arbitration timing diagram ?idle bus case figure a?0 show cycle timing diagram 16 bus arb tim idle clkout a0 a5 addr[23:0] data[15:0] a2 a3 a0 a5 br as bg bgack 47a 33 33 47a 37 47a 35 clkout s0 s41 s42 s0 s1 s2 6 addr[23:0] r/w as 8 ds 72 data[15:0] bkpt 71 70 12 9 15 18 20 show cycle start of external cycle 74 s43 16 shw cyc tim phase 1 phase 2 phase 1 phase 2 100 102 104 103 105 101 73 ipipe0 ipipe1 note: show cycles can stretch during clock phase s42 when bus accesses take longer than two cycles due to imb module wait-state insertion. .com .com .com .com 4 .com u datasheet
m68hc16zec25/d motorola 17 figure a?1 chip-select timing diagram figure a?2 reset and mode select timing diagram 16 chip sel tim 6 6 8 11 11 25 53 54 23 55 29a 29 27 46 46 14a 12 13 15 9 9 12 14 9 18 20 18 s0 s1 s2 s3 s4 s5 s0 s1 s2 s3 s4 s5 14 clkout addr[23:0] fc[2:0] siz[1:0] as ds cs r/w data[15:0] 21 17 17 16 rst/mode sel tim reset data[15:0], 75 76 77 78 modclk, bkpt .com .com .com .com 4 .com u datasheet
motorola m68hc16zec25/d 18 figure a?3 bdm serial communication timing diagram figure a?4 bdm freeze assertion timing diagram notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. table a? background debugging mode timing (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit b0 dsi input setup time t dsisu 10 ns b1 dsi input hold time t dsih 5ns b2 dsclk setup time t dscsu 10 ns b3 dsclk hold time t dsch 5ns b4 dso delay time t dsod ?0ns b5 dsclk cycle time t dsccyc 2 t cyc b6 clkout high to freeze asserted/negated t frzan ?0ns b7 clkout high to ipipe1 high impedance t ipz ?0ns b8 clkout high to ipipe1 valid t ip ?0ns b9 dsclk low time t dsclo 1 t cyc b10 ipipe1 high impedance to freeze asserted t ipfa tbd t cyc b11 freeze negated to ipipe[0:1] active t frip tbd t cyc 16 bdm ser com tim b1 b3 b2 b0 b4 clkout freeze bkpt /dsclk ipipe1/dsi ipipe0/dso b5 b9 16 bdm frz tim b8 clkout freeze ipipe1/dsi b6 b7 b11 b6 b10 .com .com .com .com 4 .com u datasheet
m68hc16zec25/d motorola 19 figure a?5 eclk timing diagram notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. 2. when previous bus cycle is not an eclk cycle, the address may be valid before eclk goes low. 3. address access time = t ecyc ?t ead ?t edsr . 4. chip select access time = t ecyc ?t ecsd ?t edsr . table a? eclk bus timing (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit e1 eclk low to address valid 2 t ead ?0ns e2 eclk low to address hold t eah 10 ns e3 eclk low to cs valid (cs delay) t ecsd 100 ns e4 eclk low to cs hold t ecsh 10 ns e5 cs negated width t ecsn 20 ns e6 read data setup time t edsr 25 ns e7 read data hold time t edhr 5ns e8 eclk low to data high impedance t edhz ?0ns e9 cs negated to data hold (read) t ecdh 0ns e10 cs negated to data high impedance t ecdz ? t cyc e11 eclk low to data valid (write) t eddw ? t cyc e12 eclk low to data hold (write) t edhw 5ns e13 address access time (read) 3 t eacc 255 ns e14 chip-select access time (read) 4 t eacs 195 ns e15 address setup time t eas 1/2 t cyc hc16 e cycle tim clkout addr[23:0] cs eclk data[15:0] e1 2a 3a e2 e5 e4 e3 e9 e7 e8 e10 e12 e14 e13 1a data[15:0] e15 e11 write read write e6 r/w .com .com .com .com 4 .com u datasheet
motorola m68hc16zec25/d 20 notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. 2. for high time, n = external sck rise time; for low time, n = external sck fall time. table a? qspi timing (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h , 200 pf load on all qspi pins) 1 num function symbol min max unit 1 operating frequency master slave f op dc dc 1/4 1/4 system clock frequency system clock frequency 2 cycle time master slave t qcyc 4 4 510 t cyc t cyc 3 enable lead time master slave t lead 2 2 128 t cyc t cyc 4 enable lag time master slave t lag 2 1/2 sck t cyc 5 clock (sck) high or low time master slave 2 t sw 2 t cyc ?30 2 t cyc ?n 255 t cyc ns ns 6 sequential transfer delay master slave (does not require deselect) t td 17 13 8192 t cyc t cyc 7 data setup time (inputs) master slave t su 20 20 ns ns 8 data hold time (inputs) master slave t hi 0 20 ns ns 9 slave access time t a ? t cyc 10 slave miso disable time t dis ? t cyc 11 data valid (after sck edge) master slave t v 50 50 ns ns 12 data hold time (outputs) master slave t ho 0 0 ns ns 13 rise time input output t ri t ro 2 30 m s ns 14 fall time input output t fi t fo 2 30 m s ns .com .com .com .com 4 .com u datasheet
m68hc16zec25/d motorola 21 figure a?6 qspi timing ?master, cpha = 0 figure a?7 qspi timing ?master, cpha = 1 16 qspi mast cpha0 13 11 6 10 12 4 4 13 12 3 2 5 1 data lsb in msb in msb out msb in msb out data lsb out port data 7 12 13 pcs[3:0] output pd miso input mosi output sck cpol=0 output sck cpol=1 output 16 qspi mast cpha1 13 11 10 12 4 4 13 12 3 2 5 1 msb pcs[3:0] output miso input msb msb out data lsb out port data 12 13 port data mosi output data lsb in msb in 7 6 1 sck cpol=0 output sck cpol=1 output .com .com .com .com 4 .com u datasheet
motorola m68hc16zec25/d 22 figure a?8 qspi timing ?slave, cpha = 0 figure a?9 qspi timing ?slave, cpha = 1 13 10 13 7 6 8 11 9 11 12 4 13 12 3 2 5 1 data lsb out pd msb out msb in msb out msb in data lsb in ss input sck cpol=0 input sck cpol=1 input miso output mosi input 4 16 qspi slv cpha0 16 qspi slv cpha1 ss input 13 12 4 12 5 11 12 6 10 9 8 data slave lsb out pd msb out msb in data lsb in 7 4 1 2 10 pd 13 3 miso output sck cpol=1 input mosi input sck cpol=0 input .com .com .com .com 4 .com u datasheet
m68hc16zec25/d motorola 23 notes: 1. below disruptive current conditions, a stressed channel will store the maximum conversion value for analog inputs greater than v rh and the minimum conversion value for inputs less than v rl . this as- sumes that v rh v dda and v rl 3 v ssa due to the presence of the sample amplifier. other channels are not affected by non-disruptive conditions 2. input signals with large slew rates or high frequency noise components cannot be converted accurate- ly. these signals also interfere with conversion of other channels. 3. exceeding limit may cause conversion error on stressed channels and on unstressed channels. transi- tions within the limit do not affect device reliability or cause permanent damage. 4. input must be current limited to the value specified. to determine the value of the required current-lim- iting resistor, calculate resistance values using positive and negative clamp values, then use the larger of the calculated values. 5. this parameter is periodically sampled rather than 100% tested. 6. applies to single pin only. 7. the values of external system components can change the maximum input current value, and affect operation. a voltage drop may occur across the external source impedances of the adjacent pins, im- pacting conversions on these adjacent pins. the actual maximum may need to be determined by test- ing the complete design. 8. current coupling is the ratio of the current induced from overvoltage (positive or negative, through an external series coupling resistor), divided by the current induced on adjacent pins. a voltage drop may occur across the external source impedances of the adjacent pins, impacting conversions on these ad- jacent pins table a?0 adc maximum ratings num parameter symbol min max unit 1 analog supply v dda ?.3 6.5 v 2 internal digital supply, with reference to v ssi v ddi ?.3 6.5 v 3 reference supply, with reference to v ssi v rh , v rl ?.3 6.5 v 4 v ss differential voltage v ssi v ssa ?.1 0.1 v 5 v dd differential voltage v ddi v dda ?.5 6.5 v 6 v ref differential voltage v rh v rl ?.5 6.5 v 7 v rh to v dda differential voltage v rh v dda ?.5 6.5 v 8 v rl to v ssa differential voltage v rl v ssa ?.5 6.5 v 9 disruptive input current 1 , 2 , 3 , 4 , 5 , 6 , 7 v negclamp @ ?.3 v v posclamp @ 8 v i na ?00 500 m a 10 positive overvoltage current coupling ratio 1, 5, 6, 8 k p 2000 11 negative overvoltage current coupling ratio 1, 5, 6, 8 k n 500 12 maximum input current 3, 4, 6 v negclamp @ ?.3 v v posclamp @ 8 v i ma ?5 25 ma .com .com .com .com 4 .com u datasheet
motorola m68hc16zec25/d 24 notes: 1. refers to operation over full temperature and frequency range. 2. to obtain full-scale, full-range results, v ssa v rl v indc v rh v dda. 3. accuracy tested and guaranteed at v rh ?v rl = 5.0 v 5%. 4. current measured at maximum system clock frequency with adc active. 5. maximum leakage occurs at maximum operating temperature. current decreases by approximately one-half for each 10 c decrease from maximum temperature. notes: 1. conversion accuracy varies with f adclk rate. reduced conversion accuracy occurs at maximum. table a?1 adc dc electrical characteristics (operating) (v ss = 0 vdc, adclk = 2.1 mhz, t a = t l to t h ) num parameter symbol min max unit 1 analog supply 1 v dda 4.5 5.5 v 2 internal digital supply 1 v ddi 4.5 5.5 v 3 v ss differential voltage v ssi ? v ssa ?1.0 1.0 mv 4 v dd differential voltage v ddi v dda ?1.0 1.0 v 5 reference voltage low 2 , 3 v rl v ssa v dda / 2 v 6 reference voltage high 2, 3 v rh v dda / 2 v dda v 7 v ref differential voltage 3 v rh v rl 4.5 5.5 v 8 input voltage 2 v indc v ssa v dda v 9 input high, port ada v ih 0.7 (v dda )v dda + 0.3 v 10 input low, port ada v il v ssa 0.3 0.2 (v dda ) v 11 analog supply current normal operation 4 low-power stop i dda 1.0 200 ma m a 12 reference supply current i ref 250 m a 13 input current, off channel 5 i off 150 na 14 total input capacitance, not sampling c inn ?0pf 15 total input capacitance, sampling c ins ?5pf table a?2 adc ac characteristics (operating) (v dd and v dda = 5.0 vdc 5%, v ss = 0 vdc, t a within operating temperature range) num parameter symbol min max unit 1 adc clock frequency f adclk 0.5 2.1 mhz 2 8-bit conversion time 1 f adclk = 1.0 mhz f adclk = 2.1 mhz t conv 15.2 7.6 m s 3 10-bit conversion time 1 f adclk = 1.0 mhz f adclk = 2.1 mhz t conv 17.1 8.6 m s 4 stop recovery time t sr ?0 m s .com .com .com .com 4 .com u datasheet
m68hc16zec25/d motorola 25 notes: 1. at v rh ? rl = 5.12 v, one 10-bit count = 5 mv and one 8-bit count = 20 mv. 2. 8-bit absolute error of 1 count (20 mv) includes 1/2 count (10 mv) inherent quantization error and 1/2 count (10 mv) circuit (differential, integral, and offset) error. 3. conversion accuracy varies with f adclk rate. reduced conversion accuracy occurs at maximum f ad- clk . assumes that minimum sample time (2 adc clocks) is selected. 4. 10-bit absolute error of 2.5 counts (12.5 mv) includes 1/2 count (2.5 mv) inherent quantization error and 2 counts (10 mv) circuit (differential, integral, and offset) error. 5. maximum source impedance is application-dependent. error resulting from pin leakage depends on junction leakage into the pin and on leakage due to charge-sharing with internal capacitance. error from junction leakage is a function of external source impedance and input leakage current. in the following expression, expected error in result value due to junction leakage (v errj ) is expressed: v errj = r s x i off where i off is a function of operating temperature, as shown in table a-11. charge-sharing leakage is a function of input source impedance, conversion rate, change in voltage between successive conversions, and the size of the decoupling capacitor used. error levels are best determined empirically. in general, continuous conversion of the same channel may not be compatible with high source impedance. table a?3 adc conversion characteristics (operating) (v dd and v dda = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h , 0.5 mhz f adclk 1.0 mhz, 2 clock input sample time) num parameter symbol min typ max unit 1 8-bit resolution 1 1 count 20 mv 2 8-bit differential nonlinearity dnl ?.5 0.5 counts 3 8-bit integral nonlinearity inl ? 1 counts 4 8-bit absolute error 2 ae ? 1 counts 5 10-bit resolution 1 1 count 5 mv 6 10-bit differential nonlinearity 3 dnl ?.5 0.5 counts 7 10-bit integral nonlinearity 3 inl ?.0 2.0 counts 8 10-bit absolute error 3, 4 ae ?.5 2.5 counts 9 source impedance at input 5 r s ?0k w .com .com .com .com 4 .com u datasheet
motorola m68hc16zec25/d 26 figure a?0 8-bit adc conversion accuracy figure a?1 10-bit adc conversion accuracy adc 8-bit accuracy 0 204060 input in mv, v rh ?v rl = 5.120 v -20 mv 8-bit absolute error boundary +20 mv 8-bit absolute error boundary b c ideal transfer curve 8-bit transfer curve (no circuit error) digital output a a b c ? +1/2 count (10 mv) inherent quantization error ? circuit-contributed +10mv error ? + 20 mv absolute error (one 8-bit count) adc 10-bit accuracy 0 204060 input in mv, v rh ?v rl = 5.120 v c a b +12.5 mv 10-bit absolute error boundary 10-bit transfer curve (no circuit error) ideal transfer curve digital output a b c ? +.5 count (2.5 mv) inherent quantization error ?circuit-contributed +10 mv error ?+12.5 mv absolute error (2.5 10-bit counts) -12.5 mv 10-bit absolute error boundary .com .com .com .com 4 .com u datasheet
m68hc16zec25/d motorola 27 notes .com .com .com .com 4 .com u datasheet
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